100
TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Peripheral Information and Electrical Specifications Copyright © 2013–2016, Texas Instruments Incorporated
7.2.6.2 Trip Zone TZ4n
This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device.
Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control
registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on
the requirements of the application.
Table 7-7. TZ4n Connections for ePWMx Modules
ePWMx
CONTROL FOR TZ4n =
NOT(EQEP1ERR OR EQEP2ERR)
CONTROL FOR TZ4n =
NOT(EQEP1ERR)
CONTROL FOR TZ4n =
NOT(EQEP2ERR)
ePWM1 PINMMR41[2:0] = 001 PINMMR41[2:0] = 010 PINMMR41[2:0] = 100
ePWM2 PINMMR41[10:8] = 001 PINMMR41[10:8] = 010 PINMMR41[10:8] = 100
ePWM3 PINMMR41[18:16] = 001 PINMMR41[18:16] = 010 PINMMR41[18:16] = 100
ePWM4 PINMMR41[26:24] = 001 PINMMR41[26:24] = 010 PINMMR41[26:24] = 100
ePWM5 PINMMR42[2:0] = 001 PINMMR42[2:0] = 010 PINMMR42[2:0] = 100
ePWM6 PINMMR42[10:8] = 001 PINMMR42[10:8] = 010 PINMMR42[10:8] = 100
ePWM7 PINMMR42[18:16] = 001 PINMMR42[18:16] = 010 PINMMR42[18:16] = 100
7.2.6.3 Trip Zone TZ5n
This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted
whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip
zone input for each ePWMx module to prevent the external system from going out of control when the
device clocks are not within expected range (system running at limp clock).
The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the
system module. These level signals are set until cleared by the application.
7.2.6.4 Trip Zone TZ6n
This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,
the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the
external system from going out of control when the CPU is stopped.
7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
A special scheme is implemented to select the actual signal used for triggering the start of conversion on
the two ADCs on this device. This scheme is defined in Section 7.5.2.3.
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