Toradex Verdin - Page 4

Verdin Carrier Board Design Guide
Preliminary – Subject to Change
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2.11.2 Unused SPI Signal Termination ......................................................................... 50
2.12 Quad Serial Peripheral Interface (Quad SPI)..................................................................... 50
2.12.1 Quad SPI Signals............................................................................................. 50
2.12.2 Unused Quad SPI Signal Termination ................................................................ 50
2.13 CAN ............................................................................................................................ 51
2.13.1 CAN Signals .................................................................................................... 51
2.13.2 Reference Schematics ...................................................................................... 51
2.13.3 Unused CAN Interface Signal Termination .......................................................... 51
2.14 PWM ........................................................................................................................... 52
2.14.1 PWM Signals ................................................................................................... 52
2.14.2 Reference Schematics ...................................................................................... 52
2.14.3 Unused PWM Signal Termination ...................................................................... 52
2.15 Inter-IC Sound (I
2
S) ....................................................................................................... 53
2.15.1 Digital Audio Signals ........................................................................................ 53
2.15.2 Reference Schematics ...................................................................................... 54
2.15.3 Unused Digital Audio Interface Signal Termination ............................................... 54
2.16 Analog Inputs ................................................................................................................ 54
2.16.1 Analog Input Signals ........................................................................................ 54
2.16.2 Unused Analog Inputs Signal Termination ........................................................... 54
2.17 General Purpose Clock Outputs ...................................................................................... 55
2.17.1 Clock Output Signals ........................................................................................ 55
2.17.2 Schematic and Layout Considerations ................................................................ 55
2.17.3 Unused Clock Output Signal Termination ............................................................ 55
2.18 GPIO ........................................................................................................................... 55
2.18.1 GPIO Signals .................................................................................................. 55
2.18.2 Unused GPIO Termination ................................................................................ 56
2.19 JTAG interface .............................................................................................................. 56
2.19.1 JTAG Signals .................................................................................................. 56
2.19.2 Reference Schematics ...................................................................................... 56
2.19.3 Unused JTAG Signal Termination ...................................................................... 57
2.20 Module Recovery .......................................................................................................... 57
2.20.1 Recovery Signals ............................................................................................. 57
2.20.2 Reference Schematics ...................................................................................... 57
2.20.3 Unused Recovery Signal Termination ................................................................. 58
3 Power Management ..................................................................................................... 59
3.1 Power Signals ............................................................................................................... 59
3.1.1 Power Supply Signals .......................................................................................... 59
3.1.2 Power Management Signals ................................................................................. 59
3.2 Module Power States ..................................................................................................... 60
3.3 General Power Sequences ............................................................................................. 62
3.3.1 “No VCC” to “Running” (startup) ............................................................................ 62
3.3.2 “Running” to “Reset” (reset) .................................................................................. 63
3.3.3 “Reset” to “Running” (startup after reset) ................................................................ 64
3.3.4 “Running” to “Sleep” (sleep).................................................................................. 65
3.3.5 “Sleep” to “Running” (wake) .................................................................................. 66
3.3.6 “Running” to “Module OFF” (shutdown) .................................................................. 67
3.3.7 “Running” to “No VCC” (force off) .......................................................................... 68
3.3.8 “Module OFF” to “Running” (startup after shutdown) ................................................ 69
3.3.9 “Module OFF” to “No VCC” (power off after shutdown) ............................................. 70
3.3.10 Remove VCC in any power state ....................................................................... 70
3.4 Power Supply Use Cases ............................................................................................... 71
3.4.1 Switched VCC Approach (Verdin Development Board) ............................................ 71
3.4.2 Minimalist Carrier Board Power Approach .............................................................. 74
3.4.3 Single Cell Battery Power Approach ...................................................................... 77
3.5 Backfeeding .................................................................................................................. 79
3.5.1 Introduction ........................................................................................................ 79
3.5.2 What is Backfeeding ............................................................................................ 80