ZED-F9P-Integration Manual
UBX-18010802 - R02
5 Hardware description Page 75 of 114
Advance Information
Figure 50: ZED-F9P USB_DM and USB_DP pins
5.3.9 Display Data Channel (DDC)
An I
2
C compliant DDC interface is available for communication with an external host CPU or u-blox
cellular modules. The interface can be operated in slave mode only. The DDC protocol and electrical
interface are fully compatible with Fast-Mode of the I
2
C industry standard. Since the maximum SCL
clock frequency is 400 kHz, the maximum transfer rate is 400 kb/s.
The I2C lines need pull up resistors. However they need to be pulled up to module VCC. This
ensures the I2C lines are not driven high before VCC is applied.
5.3.10 Antenna supervisor
An active antenna supervisor provides the means to check the antenna for open and short circuits
and to shut off the antenna supply if a short circuit is detected. The Antenna Supervisor is
configured using serial port UBX binary protocol message. Once enabled, the active antenna
supervisor produces status messages, reporting in NMEA and/or UBX binary protocol.
The current setting of the active antenna supervisor can also be checked by polling the related CFG-
HW-ANT-* command.
The current active antenna status can be determined by polling the UBX-MON-RF command. If an
antenna is connected, the initial state after power-up is “Active Antenna OK" in the u-center UBX-
MON-RF view.
The module firmware supports an active antenna supervisor circuit, which is connected to the
ANT_DET, ANT_OFF, ANT_SHORT_N pins. For an example the open circuit detection circuit using
ANT_DET, "high" = Antenna detected (antenna consumes current); "low" = Antenna not detected
(no current drawn).
The following picture details the required circuit and the sections following it detail how to enable
and monitor each feature:
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