ZED-F9P-Integration Manual
UBX-18010802 - R02
4 Receiver description Page 35 of 114
Advance Information
The USB interface supports one power mode:
•
In Self Powered Mode the receiver is powered by its own power supply. V_USB is used to detect
the availability of the USB port, i.e. whether the receiver is connected to a USB host.
USB Bus powered mode is not supported.
The voltage range for V_USB is specified from 3.0 V to 3.6 V, which differs slightly from the
specification for VCC.
The boot screen is retransmitted on the USB port after the enumeration. However, messages
generated between boot-up of the receiver and USB enumeration are not visible on the USB
port.
4.5.5 DDC Port
The Display Data Channel (DDC) bus is a two-wire communication interface compatible with the
I²C
standard (Integrated Circuit). See our on-line product selector matrix for availability.
Unlike all other interfaces, the DDC is not able to communicate in full-duplex mode, i.e. TX and RX
are mutually exclusive. u-blox receivers act as a slave in the communication setup, therefore they
cannot initiate data transfers on their own. The host, which is always master, provides the data
clock (SCL), and the clock frequency is therefore not configurable on the slave.
The receiver's DDC address is set to 0x42 by default.
As the receiver will be run in slave mode and the DDC physical layer lacks a handshake mechanism
to inform the master about data availability, a layer has been inserted between the physical layer
and the UBX and NMEA layer. The receiver DDC interface implements a simple streaming interface
that allows the constant polling of data, discarding everything that is not parse-able. The receiver
returns 0xFF if no data is available. The TX-ready feature can be used to inform the master about
data availability and can be used as a trigger for data transmission.
4.5.5.1 Read Access
The DDC interface allows 256 slave registers to be addressed. As shown in Figure DDC Register
Layout only three of these are currently implemented. The data registers 0 to 252, at addresses 0x00
to 0xFC, each 1 byte in size, contain information to be defined later - the result of reading them is
undefined. The currently available number of bytes in the message stream can be read at addresses
0xFD and 0xFE. The register at address 0xFF allows the data stream to be read. If there is no data
awaiting transmission from the receiver, then this register will deliver the value 0xff, which cannot
be the first byte of a valid message. If message data is ready for transmission, then successive reads
of register 0xff will deliver the waiting message data.
The registers 0x00 to 0xFC are reserved for future use and may be defined in a later firmware
release. Do not use them, as they don't provide any meaningful data!
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