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Valleylab LigaSure - Shared RAM; I;0 Expansion; Keyboard Interface and Activation Inputs; Power Supply Supervisor Circuit

Valleylab LigaSure
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Control Board
5-6 LigaSure Vessel Sealing Generator Service Manual
Shared RAM
An IDT 713425A device (U4) with semaphore flags provides the 4K x 8 external
shared static RAM. The shared RAM allows the main microcontroller (U5) and
the feedback microcontroller (U11) to share common variables. It functions as a
communications interface between the main and feedback microcontrollers. It
also provides additional general-purpose RAM to these microcontrollers.
I/0 Expansion
Three devices provide input/output (I/O) expansion capabilities:
One ST Microelectronics PSD835G2 programmable systems device (U6)
One ST Microelectronics PSD835G2 programmable systems device (U3)
One 82C55 expansion port (U2)
The ST Microelectronics PSD835G2 incorporates 52 individually programmable
I/O pins divided into 6 ports of 8-bits each and 1 port of 4-bits. Of the general I/O
pins, 24 can alternatively be utilized for 24 PLD outputs. The PSD835G2 also
contains 512K x 8 Main Flash Memory, 32K x 8 Boot Flash Memory, 2K x 8 of
SRAM, and a power management unit for battery backup. The power
management unit for battery backup is not used by the Feedback microcontroller.
The I/O expansion capabilities of the Feedback PSD835G2 has a built-in IEEE
1149.1 compliant JTAG serial port to allow full-chip in-System Programmability
(ISP). The Main PSD835G2 is #1 on the JTAG chain and the Feedback
PSD835G2 with the exception that the 512K x 8 Flash Memory for the Main
PSD835G2 is accessed in a bank switching methodology and the I/O expansion
capabilities are configured as outputs for lamp control, keyboard scanning, and
chip selects.
The 82C55 is a generic I/O expander which incorporates 24 I/O pins divided into
3 ports of 8-bits each. The 82C55 is configured as all inputs, and is used to read
the keyboard, keying signals, accessory switches, and system status flags.
Keyboard Interface and Activation Inputs
The keyboard interface is a simple row and column matrix between three bank
select output lines (BANK0–BANK2) on port A of the PSD835G2 (U3). The
main microcontroller and eight keyboard (KBD_D0–KBD_D7) input lines on
port A of the expansion port 82C55 (U2) use this interface.
Port B of the expansion port 82C55 reads activation inputs from the IsoBloc
decoding circuits on the RF board.
Power Supply Supervisor Circuit
The power supply supervisor circuit (U14), a MAX691, generates a Reset signal
and a Reset\ signal for the main microcontroller (U5) if the power supply voltage
to the control board drops below 4.65 V. It also generates a voltage sensitive chip
select for the PSD835G2 (U6) and the PSD835G2 (U3). The low voltage
threshold (4.65 V) places U3 and U6 in sleep mode and disables the 2K x 8
external static RAM.
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