Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 175
UG482 (v1.9) December 19, 2016
RX Buffer Bypass
RXPHDLYPD In Async RX phase and delay alignment circuit
power down. Tied High when a) RX
buffer bypass is not in use;
b) RXPD is asserted or
c) RXOUTCLKSEL is set to 3'b010
but the recovered clock is not available.
Tied Low during RX buffer bypass mode
normal operation.
0: Power-up the RX phase and delay
alignment circuit.
1: Power-down the RX phase and
delay alignment circuit.
RXPHOVRDEN In Async RX phase alignment counter override
enable. Tied Low when not in use.
0: Normal operation.
1: Enables the RX phase alignment
counter override with the
RXPH_CFG[10:6] value.
RXDLYSRESET In Async RX delay alignment soft reset to
gradually shift RXUSRCLK to the center
of the delay alignment tap. The delay
alignment tap has a full range of ±4 ns
and a half range of ±2 ns. This soft reset
can be used to initiate the GTP
transceiver to perform the RX phase and
delay alignment automatically when all
other RX bypass buffer input ports are
Low.
RXDLYBYPASS In Async RX delay alignment bypass.
0: Uses the RX delay alignment
circuit.
1: Bypasses the RX delay alignment
circuit.
RXDLYEN In Async RX delay alignment enable. Tied Low
when not in use.
RXDLYOVRDEN In Async RX delay alignment counter override
enable. Tied Low when not in use.
0: Normal operation.
1: Enables the RX delay alignment
counter override with the
RXDLY_CFG[14:6] value.
RXDDIEN In Async RX data delay insertion enable in the
deserializer. Set High in RX buffer
bypass mode.
Table 4-29: RX Buffer Bypass Ports (Cont’d)
Port Dir Clock Domain Description
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English