Xilinx 7 Series - Page 289

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 289
UG482 (v1.9) December 19, 2016
0041
(Cont’d)
12:8 R/W RX_SIG_VALID_DLY 4:0
32
43
54
65
76
87
98
10 9
11 10
12 11
13 12
14 13
15 14
16 15
17 16
18 17
19 18
20 19
21 20
22 21
23 22
24 23
25 24
26 25
27 26
28 27
29 28
30 29
31 30
32 31
0041 7 R/W ALIGN_PCOMMA_DET 0
FALSE 0
TRUE 1
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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