Xilinx 7 Series

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 297
UG482 (v1.9) December 19, 2016
0053
(Cont’d)
15:12 R/W CHAN_BOND_MAX_SKEW 3:0
77
88
99
10 10
11 11
12 12
13 13
14 14
0053 9:0 R/W CHAN_BOND_SEQ_2_4 9:0 0-1023 0-1023
0054 15:0 R/W RXDLY_TAP_CFG 15:0 0-65535 0-65535
0055 15:0 R/W RXDLY_CFG 15:0 0-65535 0-65535
0057 12:8 R/W RXPH_MONITOR_SEL 4:0 0-31 0-31
0057 5:0 R/W RX_DDI_SEL 5:0 0-63 0-63
0059 7R/W TX_XCLK_SEL 0
TXOUT 0
TXUSR 1
0059 6R/W RXBUF_EN 0
FALSE 0
TRUE 1
005A 9R/W TXOOB_CFG 0 0-1 0-1
005A 8 R/W LOOPBACK_CFG 0 0-1 0-1
005D 10:8 R/W TXPI_CFG5 2:0 0-7 0-7
005D 7 R/W TXPI_CFG4 0 0-1 0-1
005D 6 R/W TXPI_CFG3 0 0-1 0-1
005D 5:4 R/W TXPI_CFG2 1:0 0-3 0-3
005D 3:2 R/W TXPI_CFG1 1:0 0-3 0-3
005D 1:0 R/W TXPI_CFG0 1:0 0-3 0-3
005E 15:14 R/W SATA_PLL_CFG 1:0
VCO_3000MHZ
0
VCO_1500MHZ
1
VCO_750MHZ
2
0060 15:0 R/W TXPHDLY_CFG 15:0 0-65535 0-65535
0061 7:0 R/W TXPHDLY_CFG 23:16 0-255 0-255
0062 15:0 R/W TXDLY_CFG 15:0 0-65535 0-65535
0063 15:0 R/W TXDLY_TAP_CFG 15:0 0-65535 0-65535
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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