Xilinx 7 Series - Page 298

298 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Appendix D: DRP Address Map of the GTP Transceiver
0064 15:0 R/W TXPH_CFG 15:0 0-65535 0-65535
0065 12:8 R/W TXPH_MONITOR_SEL 4:0 0-31 0-31
0066 15:0 R/W RX_BIAS_CFG 15:0 0-65535 0-65535
0068 3 R/W RXOOB_CLK_CFG 0
PMA 0
FABRIC 1
0068 1 R/W TX_CLKMUX_EN 0 0-1 0-1
0068 0 R/W RX_CLKMUX_EN 0 0-1 0-1
0069 14:0 R/W TERM_RCAL_CFG 14:0 0-32767 0-32767
006A 15:13 R/W TERM_RCAL_OVRD 2:0 0-7 0-7
006A 4:0 R/W TX_CLK25_DIV 4:0
10
21
32
43
54
65
76
87
98
10 9
11 10
12 11
13 12
14 13
15 14
16 15
17 16
18 17
19 18
20 19
21 20
22 21
23 22
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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