Xilinx 7 Series - Page 299

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 299
UG482 (v1.9) December 19, 2016
006A
(Cont’d)
4:0 R/W TX_CLK25_DIV 4:0
24 23
25 24
26 25
27 26
28 27
29 28
30 29
31 30
32 31
006B 15 R/W PMA_RSV5 0 0-1 0-1
006B 11:8 R/W PMA_RSV4 3:0 0-15 0-15
006B 2:0 R/W TX_DATA_WIDTH 2:0
16 2
20 3
32 4
40 5
006F 15:0 R/W PCS_RSVD_ATTR 15:0 0-65535 0-65535
0070 15:0 R/W PCS_RSVD_ATTR 31:16 0-65535 0-65535
0071 15:0 R/W PCS_RSVD_ATTR 47:32 0-65535 0-65535
0075 14:8 R/W TX_MARGIN_FULL_1 6:0 0-127 0-127
0075 6:0 R/W TX_MARGIN_FULL_0 6:0 0-127 0-127
0076 14:8 R/W TX_MARGIN_FULL_3 6:0 0-127 0-127
0076 6:0 R/W TX_MARGIN_FULL_2 6:0 0-127 0-127
0077 14:8 R/W TX_MARGIN_LOW_0 6:0 0-127 0-127
0077 6:0 R/W TX_MARGIN_FULL_4 6:0 0-127 0-127
0078 14:8 R/W TX_MARGIN_LOW_2 6:0 0-127 0-127
0078 6:0 R/W TX_MARGIN_LOW_1 6:0 0-127 0-127
0079 14:8 R/W TX_MARGIN_LOW_4 6:0 0-127 0-127
0079 6:0 R/W TX_MARGIN_LOW_3 6:0 0-127 0-127
007A 13:8 R/W TX_DEEMPH1 5:0 0-63 0-63
007A 5:0 R/W TX_DEEMPH0 5:0 0-63 0-63
007C 10:8 R/W TX_RXDETECT_REF 2:0 0-7 0-7
007C 3 R/W TX_MAINCURSOR_SEL 0 0-1 0-1
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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