Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 51
UG482 (v1.9) December 19, 2016
Reset and Initialization
Table 2-19 lists the attributes required by GTP transceiver’s RX initialization. In general cases, the
reset time required by each reset on the RX datapath varies depending on line rate and function. The
factors affecting each reset time are user-configurable attributes listed in Table 2-19.
RXBUFRESET In Async This port is driven High and then deasserted to
start the RX elastic buffer reset process. In
either single mode or sequential mode,
activating RXBUFRESET resets the RX elastic
buffer only.
RXUSERRDY In Async This port is driven High from the user's
application when RXUSRCLK and
RXUSRCLK2 are stable. For example, if an
MMCM is used to generate both RXUSRCLK
and RXUSRCLK2, then the MMCM lock
signal can be used here.
RXRESETDONE Out RXUSRCLK2 When asserted, this active-High signal
indicates the GTP transceiver’s RX has
finished reset and is ready for use. This port is
driven Low when GTRXRESET is driven
High. This signal is not driven High until
RXUSERRDY goes High.
RXPMARESETDONE Out Async This active-High signal indicates GTP RX
PMA reset is complete. This port is driven Low
when GTRXRESET or RXPMARESET is
asserted.
RXOOBRESET In Async This port can be used to reset the OOB
individually. It should be tied Low if the OOB
function is not used or the OOB single reset is
not required.
RXOOBRESET is independent from the GTP
transceiver’s RX reset state machine sequence
as shown in Figure 2-18. Sequential mode and
single mode do not apply to RXOOBRESET.
Activating RXOOBRESET does not cause
RXRESETDONE to transition from Low to
High or High to Low.
Table 2-19: RX Initialization and Reset Attributes
Attribute Type Description
RXOSCALRESET_TIME 5-bit Binary Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used. Must be a non-zero value when GTRXRESET
is used to initiate the reset process.
RXOSCALRESET_TIMEOUT 5-bit Binary Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used. Must be a non-zero value when GTRXRESET
is used to initiate the reset process.
Table 2-18: RX Initialization and Reset Ports (Cont’d)
Port Dir Clock Domain Description
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600