Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x286 [15:0] R/W CH1_TX_PCS_CFG3 [15:0] 0–65535 0–65535
0x287 [15:0] R/W CH1_TX_PCS_CFG4 [15:0] 0–65535 0–65535
0x288 [15:0] R/W CH1_TX_PCS_CFG5 [15:0] 0–65535 0–65535
0x289 [15:0] R/W CH1_TX_PCS_CFG6 [15:0] 0–65535 0–65535
0x28a [15:0] R/W CH1_TX_PCS_CFG7 [15:0] 0–65535 0–65535
0x28b [15:0] R/W CH1_TX_PCS_CFG8 [15:0] 0–65535 0–65535
0x28c [15:0] R/W CH1_TX_PCS_CFG9 [15:0] 0–65535 0–65535
0x28d [15:0] R/W CH1_TX_PCS_CFG10 [15:0] 0–65535 0–65535
0x28e [15:0] R/W CH1_TX_PCS_CFG11 [15:0] 0–65535 0–65535
0x28f [15:0] R/W CH1_TX_PCS_CFG12 [15:0] 0–65535 0–65535
0x290 [15:0] R/W CH1_TX_PCS_CFG13 [15:0] 0–65535 0–65535
0x291 [15:0] R/W CH1_TX_PCS_CFG14 [15:0] 0–65535 0–65535
0x292 [15:0] R/W CH1_TX_PCS_CFG15 [15:0] 0–65535 0–65535
0x293 [15:0] R/W CH1_TX_PCS_CFG16 [15:0] 0–65535 0–65535
0x294 [15:0] R/W CH1_TX_PCS_CFG17 [15:0] 0–65535 0–65535
0x295 [15:0] R/W CH1_A_CH_CFG0 [15:0] 0–65535 0–65535
0x296 [15:0] R/W CH1_A_CH_CFG1 [15:0] 0–65535 0–65535
0x297 [15:0] R/W CH1_A_CH_CFG2 [15:0] 0–65535 0–65535
0x298 [15:0] R/W CH1_A_CH_CFG3 [15:0] 0–65535 0–65535
0x299 [15:0] R/W CH1_A_CH_CFG4 [15:0] 0–65535 0–65535
0x29a [15:0] R/W CH1_A_CH_CFG5 [15:0] 0–65535 0–65535
0x29b [15:0] R/W CH1_A_CH_CFG6 [15:0] 0–65535 0–65535
0x2a0 [15:0] R/W CH1_RST_TIME_CFG0 [15:0] 0–65535 0–65535
0x2a1 [15:0] R/W CH1_RST_TIME_CFG1 [15:0] 0–65535 0–65535
0x2a2 [15:0] R/W CH1_RST_TIME_CFG2 [15:0] 0–65535 0–65535
0x2a3 [15:0] R/W CH1_RST_TIME_CFG3 [15:0] 0–65535 0–65535
0x2a4 [15:0] R/W CH1_RST_TIME_CFG4 [15:0] 0–65535 0–65535
0x2a5 [15:0] R/W CH1_RST_TIME_CFG5 [15:0] 0–65535 0–65535
0x2a6 [15:0] R/W CH1_RST_TIME_CFG6 [15:0] 0–65535 0–65535
0x2a7 [15:0] R/W CH1_RST_LP_ID_CFG0 [15:0] 0–65535 0–65535
0x2a8 [15:0] R/W CH1_RST_LP_ID_CFG1 [15:0] 0–65535 0–65535
0x2a9 [15:0] R/W CH1_RST_LP_CFG0 [15:0] 0–65535 0–65535
0x2aa [15:0] R/W CH1_RST_LP_CFG1 [15:0] 0–65535 0–65535
0x2ab [15:0] R/W CH1_RST_LP_CFG2 [15:0] 0–65535 0–65535
0x2ac [15:0] R/W CH1_RST_LP_CFG3 [15:0] 0–65535 0–65535
0x2ad [15:0] R/W CH1_RST_LP_CFG4 [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 142
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Xilinx Virtex UltraScale+ FPGAs Specifications

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Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English