Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x24b [15:0] R/W CH1_RX_APT_CFG20B [15:0] 0–65535 0–65535
0x24c [15:0] R/W CH1_RX_APT_CFG21A [15:0] 0–65535 0–65535
0x24d [15:0] R/W CH1_RX_APT_CFG21B [15:0] 0–65535 0–65535
0x24e [15:0] R/W CH1_RX_APT_CFG28A [15:0] 0–65535 0–65535
0x24f [15:0] R/W CH1_RX_APT_CFG28B [15:0] 0–65535 0–65535
0x250 [15:0] R/W CH1_RX_APT_CFG22A [15:0] 0–65535 0–65535
0x251 [15:0] R/W CH1_RX_APT_CFG22B [15:0] 0–65535 0–65535
0x252 [15:0] R/W CH1_RX_APT_CFG23A [15:0] 0–65535 0–65535
0x253 [15:0] R/W CH1_RX_APT_CFG23B [15:0] 0–65535 0–65535
0x254 [15:0] R/W CH1_RX_APT_CFG24A [15:0] 0–65535 0–65535
0x255 [15:0] R/W CH1_RX_APT_CFG24B [15:0] 0–65535 0–65535
0x256 [15:0] R/W CH1_RX_APT_CFG25A [15:0] 0–65535 0–65535
0x257 [15:0] R/W CH1_RX_APT_CFG25B [15:0] 0–65535 0–65535
0x258 [15:0] R/W CH1_RX_APT_CFG26A [15:0] 0–65535 0–65535
0x259 [15:0] R/W CH1_RX_APT_CFG26B [15:0] 0–65535 0–65535
0x25a [15:0] R/W CH1_RX_APT_CFG27A [15:0] 0–65535 0–65535
0x25b [15:0] R/W CH1_RX_APT_CFG27B [15:0] 0–65535 0–65535
0x25c [15:0] R/W CH1_RX_DSP_CFG [15:0] 0–65535 0–65535
0x264 [15:0] R/W CH1_RX_CAL_CFG2A [15:0] 0–65535 0–65535
0x265 [15:0] R/W CH1_RX_CAL_CFG2B [15:0] 0–65535 0–65535
0x267 [15:0] R/W CH1_RX_CAL_CFG0A [15:0] 0–65535 0–65535
0x268 [15:0] R/W CH1_RX_CAL_CFG0B [15:0] 0–65535 0–65535
0x269 [15:0] R/W CH1_RX_CAL_CFG1A [15:0] 0–65535 0–65535
0x26a [15:0] R/W CH1_RX_CAL_CFG1B [15:0] 0–65535 0–65535
0x26b [15:0] R/W CH1_RX_ADC_CFG0 [15:0] 0–65535 0–65535
0x26c [15:0] R/W CH1_RX_ADC_CFG1 [15:0] 0–65535 0–65535
0x26e [15:0] R/W CH1_RX_CLKGN_CFG0 [15:0] 0–65535 0–65535
0x26f [15:0] R/W CH1_RX_CTLE_CFG0 [15:0] 0–65535 0–65535
0x270 [15:0] R/W CH1_RX_CTLE_CFG1 [15:0] 0–65535 0–65535
0x271 [15:0] R/W CH1_RX_CTLE_CFG2 [15:0] 0–65535 0–65535
0x272 [15:0] R/W CH1_RX_CTLE_CFG3 [15:0] 0–65535 0–65535
0x280 [15:0] R/W CH1_RX_PCS_CFG0 [15:0] 0–65535 0–65535
0x281 [15:0] R/W CH1_RX_PCS_CFG1 [15:0] 0–65535 0–65535
0x282 [15:0] R/W CH1_RX_MON_CFG [15:0] 0–65535 0–65535
0x283 [15:0] R/W CH1_TX_PCS_CFG0 [15:0] 0–65535 0–65535
0x284 [15:0] R/W CH1_TX_PCS_CFG1 [15:0] 0–65535 0–65535
0x285 [15:0] R/W CH1_TX_PCS_CFG2 [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 141
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English