Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x226 [15:0] R/W CH1_RX_APT_CFG2A [15:0] 0–65535 0–65535
0x227 [15:0] R/W CH1_RX_APT_CFG2B [15:0] 0–65535 0–65535
0x228 [15:0] R/W CH1_RX_APT_CFG3A [15:0] 0–65535 0–65535
0x229 [15:0] R/W CH1_RX_APT_CFG3B [15:0] 0–65535 0–65535
0x22a [15:0] R/W CH1_RX_APT_CFG4A [15:0] 0–65535 0–65535
0x22b [15:0] R/W CH1_RX_APT_CFG4B [15:0] 0–65535 0–65535
0x22c [15:0] R/W CH1_RX_APT_CFG5A [15:0] 0–65535 0–65535
0x22d [15:0] R/W CH1_RX_APT_CFG5B [15:0] 0–65535 0–65535
0x22e [15:0] R/W CH1_RX_APT_CFG6A [15:0] 0–65535 0–65535
0x22f [15:0] R/W CH1_RX_APT_CFG6B [15:0] 0–65535 0–65535
0x230 [15:0] R/W CH1_RX_APT_CFG7A [15:0] 0–65535 0–65535
0x231 [15:0] R/W CH1_RX_APT_CFG7B [15:0] 0–65535 0–65535
0x232 [15:0] R/W CH1_RX_APT_CFG8A [15:0] 0–65535 0–65535
0x233 [15:0] R/W CH1_RX_APT_CFG8B [15:0] 0–65535 0–65535
0x234 [15:0] R/W CH1_RX_APT_CFG9A [15:0] 0–65535 0–65535
0x235 [15:0] R/W CH1_RX_APT_CFG9B [15:0] 0–65535 0–65535
0x236 [15:0] R/W CH1_RX_APT_CFG10A [15:0] 0–65535 0–65535
0x237 [15:0] R/W CH1_RX_APT_CFG10B [15:0] 0–65535 0–65535
0x238 [15:0] R/W CH1_RX_APT_CFG11A [15:0] 0–65535 0–65535
0x239 [15:0] R/W CH1_RX_APT_CFG11B [15:0] 0–65535 0–65535
0x23a [15:0] R/W CH1_RX_APT_CFG12A [15:0] 0–65535 0–65535
0x23b [15:0] R/W CH1_RX_APT_CFG12B [15:0] 0–65535 0–65535
0x23c [15:0] R/W CH1_RX_APT_CFG13A [15:0] 0–65535 0–65535
0x23d [15:0] R/W CH1_RX_APT_CFG13B [15:0] 0–65535 0–65535
0x23e [15:0] R/W CH1_RX_APT_CFG14A [15:0] 0–65535 0–65535
0x23f [15:0] R/W CH1_RX_APT_CFG14B [15:0] 0–65535 0–65535
0x240 [15:0] R/W CH1_RX_APT_CFG15A [15:0] 0–65535 0–65535
0x241 [15:0] R/W CH1_RX_APT_CFG15B [15:0] 0–65535 0–65535
0x242 [15:0] R/W CH1_RX_APT_CFG16A [15:0] 0–65535 0–65535
0x243 [15:0] R/W CH1_RX_APT_CFG16B [15:0] 0–65535 0–65535
0x244 [15:0] R/W CH1_RX_APT_CFG17A [15:0] 0–65535 0–65535
0x245 [15:0] R/W CH1_RX_APT_CFG17B [15:0] 0–65535 0–65535
0x246 [15:0] R/W CH1_RX_APT_CFG18A [15:0] 0–65535 0–65535
0x247 [15:0] R/W CH1_RX_APT_CFG18B [15:0] 0–65535 0–65535
0x248 [15:0] R/W CH1_RX_APT_CFG19A [15:0] 0–65535 0–65535
0x249 [15:0] R/W CH1_RX_APT_CFG19B [15:0] 0–65535 0–65535
0x24a [15:0] R/W CH1_RX_APT_CFG20A [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 140
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English