Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x201 [15:0] R/W CH1_TX_DRV_CFG0 [15:0] 0–65535 0–65535
0x202 [15:0] R/W CH1_TX_DRV_CFG1 [15:0] 0–65535 0–65535
0x203 [15:0] R/W CH1_TX_DRV_CFG2 [15:0] 0–65535 0–65535
0x204 [15:0] R/W CH1_TX_ANA_CFG1 [15:0] 0–65535 0–65535
0x205 [15:0] R/W CH1_TX_ANA_CFG2 [15:0] 0–65535 0–65535
0x206 [15:0] R/W CH1_TX_ANA_CFG3 [15:0] 0–65535 0–65535
0x207 [15:0] R/W CH1_TX_DRV_CFG3 [15:0] 0–65535 0–65535
0x208 [15:0] R/W CH1_TX_DRV_CFG4 [15:0] 0–65535 0–65535
0x209 [15:0] R/W CH1_TX_DRV_CFG5 [15:0] 0–65535 0–65535
0x20a [15:0] R/W CH1_TX_LPBK_CFG0 [15:0] 0–65535 0–65535
0x20b [15:0] R/W CH1_TX_LPBK_CFG1 [15:0] 0–65535 0–65535
0x20c [15:0] R/W CH1_TX_ANA_CFG4 [15:0] 0–65535 0–65535
0x20d [15:0] R/W CH1_TX_CAL_CFG0 [15:0] 0–65535 0–65535
0x20e [15:0] R/W CH1_TX_CAL_CFG1 [15:0] 0–65535 0–65535
0x20f [15:0] R/W CH1_TX_ANA_CFG0 [15:0] 0–65535 0–65535
0x210 [15:0] R/W CH1_RX_ANA_CFG0 [15:0] 0–65535 0–65535
0x211 [15:0] R/W CH1_RX_ANA_CFG1 [15:0] 0–65535 0–65535
0x212 [15:0] R/W CH1_RX_PAD_CFG0 [15:0] 0–65535 0–65535
0x213 [15:0] R/W CH1_RX_PAD_CFG1 [15:0] 0–65535 0–65535
0x214 [15:0] R/W CH1_RX_CDR_CFG4A [15:0] 0–65535 0–65535
0x215 [15:0] R/W CH1_RX_CDR_CFG4B [15:0] 0–65535 0–65535
0x216 [15:0] R/W CH1_RX_CDR_CFG3A [15:0] 0–65535 0–65535
0x217 [15:0] R/W CH1_RX_CDR_CFG3B [15:0] 0–65535 0–65535
0x218 [15:0] R/W CH1_RX_CDR_CFG2A [15:0] 0–65535 0–65535
0x219 [15:0] R/W CH1_RX_CDR_CFG2B [15:0] 0–65535 0–65535
0x21a [15:0] R/W CH1_RX_CDR_CFG1A [15:0] 0–65535 0–65535
0x21b [15:0] R/W CH1_RX_CDR_CFG1B [15:0] 0–65535 0–65535
0x21c [15:0] R/W CH1_RX_CDR_CFG0A [15:0] 0–65535 0–65535
0x21d [15:0] R/W CH1_RX_CDR_CFG0B [15:0] 0–65535 0–65535
0x21e [15:0] R/W CH1_RX_CLKGN_CFG1 [15:0] 0–65535 0–65535
0x21f [15:0] R/W CH1_RX_ANA_CFG2 [15:0] 0–65535 0–65535
0x220 [15:0] R/W CH1_RX_APT_CTRL_CFG2 [15:0] 0–65535 0–65535
0x221 [15:0] R/W CH1_RX_APT_CTRL_CFG3 [15:0] 0–65535 0–65535
0x222 [15:0] R/W CH1_RX_APT_CFG0A [15:0] 0–65535 0–65535
0x223 [15:0] R/W CH1_RX_APT_CFG0B [15:0] 0–65535 0–65535
0x224 [15:0] R/W CH1_RX_APT_CFG1A [15:0] 0–65535 0–65535
0x225 [15:0] R/W CH1_RX_APT_CFG1B [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 139
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English