Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x0c3 [15:0] R/W DRPEN_CFG [15:0] 0–65535 0–65535
0x0d0 [15:0] R/W FEC_CFG0 [15:0] 0–65535 0–65535
0x0d1 [15:0] R/W FEC_CFG1 [15:0] 0–65535 0–65535
0x0d2 [15:0] R/W FEC_CFG2 [15:0] 0–65535 0–65535
0x0d3 [15:0] R/W FEC_CFG3 [15:0] 0–65535 0–65535
0x0d4 [15:0] R/W FEC_CFG4 [15:0] 0–65535 0–65535
0x0d5 [15:0] R/W FEC_CFG5 [15:0] 0–65535 0–65535
0x0d6 [15:0] R/W FEC_CFG6 [15:0] 0–65535 0–65535
0x0d7 [15:0] R/W FEC_CFG7 [15:0] 0–65535 0–65535
0x0d8 [15:0] R/W FEC_CFG8 [15:0] 0–65535 0–65535
0x0d9 [15:0] R/W FEC_CFG9 [15:0] 0–65535 0–65535
0x0da [15:0] R/W FEC_CFG10 [15:0] 0–65535 0–65535
0x0db [15:0] R/W FEC_CFG11 [15:0] 0–65535 0–65535
0x0dc [15:0] R/W FEC_CFG12 [15:0] 0–65535 0–65535
0x0dd [15:0] R/W FEC_CFG13 [15:0] 0–65535 0–65535
0x0de [15:0] R/W FEC_CFG14 [15:0] 0–65535 0–65535
0x0df [15:0] R/W FEC_CFG15 [15:0] 0–65535 0–65535
0x0e0 [15:0] R/W FEC_CFG16 [15:0] 0–65535 0–65535
0x0e1 [15:0] R/W FEC_CFG17 [15:0] 0–65535 0–65535
0x0e2 [15:0] R/W FEC_CFG18 [15:0] 0–65535 0–65535
0x0e3 [15:0] R/W FEC_CFG19 [15:0] 0–65535 0–65535
0x0e4 [15:0] R/W FEC_CFG20 [15:0] 0–65535 0–65535
0x0e5 [15:0] R/W FEC_CFG21 [15:0] 0–65535 0–65535
0x0e6 [15:0] R/W FEC_CFG22 [15:0] 0–65535 0–65535
0x0e7 [15:0] R/W FEC_CFG23 [15:0] 0–65535 0–65535
0x0e8 [15:0] R/W FEC_CFG24 [15:0] 0–65535 0–65535
0x0e9 [15:0] R/W FEC_CFG25 [15:0] 0–65535 0–65535
0x0ea [15:0] R/W FEC_CFG26 [15:0] 0–65535 0–65535
0x0eb [15:0] R/W FEC_CFG27 [15:0] 0–65535 0–65535
0x15e [15:0] R/W BIAS_CFG0 [15:0] 0–65535 0–65535
0x15f [15:0] R/W BIAS_CFG1 [15:0] 0–65535 0–65535
0x160 [15:0] R/W BIAS_CFG2 [15:0] 0–65535 0–65535
0x161 [15:0] R/W BIAS_CFG3 [15:0] 0–65535 0–65535
0x162 [15:0] R/W BIAS_CFG4 [15:0] 0–65535 0–65535
0x163 [15:0] R/W BIAS_CFG5 [15:0] 0–65535 0–65535
0x164 [15:0] R/W BIAS_CFG6 [15:0] 0–65535 0–65535
0x165 [15:0] R/W BIAS_CFG7 [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 138
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English