Xilinx Virtex UltraScale+ FPGAs User Manual

Table 19: Recommended Receiver Resets for Common Situations (cont'd)
Situation
Components
to be Reset
Recommended RX Reset Setting
RXRESETMODE RXPMARESETMASK RXPCSRESETMASK
1
After connecting RXN/RXP Entire RX
2'b00 8’b11111111 4’b1111
After recovered clock
becomes stable
RX PCS
2'b11 8’b00000000 4’b1111
After RX elastic buffer error RX PCS
2'b11 8’b00000000 4’b1111
After PRBS error
PRBS Error
Counter
2'b11 8’b00000000 4’b1000
Eye Scan reset only Eye Scan
2'b11 8’b00000000 4’b0001
Notes:
1. RXPCSRESETMASK[1] can be set to 0 if the FEC is bypassed.
After Power-up and Configuration
The PLL being used and the enre GTM RX require a reset aer conguraon. See GTM
Transceiver RX Reset in Response to Compleon of Conguraon.
After Turning on a Reference Clock to the PLL Being
Used
If the reference clock(s) changes or GTM transceiver(s) are powered up aer conguraon,
perform a full RX sequenal reset aer the PLL fully completes its reset procedure.
After Changing the Reference Clock to the PLL Being
Used
Whenever the reference clock input to the PLL is changed, the PLL must be reset aerwards to
ensure that it locks to the new frequency. Perform a full RX sequenal reset aer the PLL fully
completes its reset procedure.
After Assertion/Deassertion of PLLPD for the PLL
Being Used
When the PLL being used goes back to normal operaon aer power down, the PLL must be
reset. Perform a full RX sequenal reset aer the PLL fully completes its reset procedure.
After Assertion/Deassertion of RXPD
Aer the RXPD signal is deasserted, perform a full RX sequenal reset.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 43
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English