Xilinx Virtex UltraScale+ FPGAs User Manual

RX Rate Change
When a rate change is performed, a full RX sequenal reset is required aer the rate aributes
have been updated.
RX Parallel Clock Source Reset
The clocks driving RXUSRCLK must be stable for correct operaon. Perform an RX PCS reset
aer the clock source re-locks.
After Remote Power-Up
If the source of incoming data is powered up aer the GTM transceiver that is receiving its data
has begun operang, a full RX sequenal reset must be performed to ensure a clean lock to the
incoming data.
After Connecting RXN/RXP
When the RX data to the GTM transceiver comes from a connector that can be plugged in and
unplugged, a full RX sequenal reset must be performed when the data source is plugged in to
ensure that it can lock to incoming data.
After Recovered Clock Becomes Stable
Depending on the design of the clocking scheme, it is possible for the RX reset sequence to be
completed before the CDR is locked to the incoming data. In this case, the recovered clock might
not be stable when RXRESETDONE is asserted. When the RX buer is used, a single mode reset
targeng the RX elasc buer must be triggered aer the recovered clock becomes stable.
Refer to the UltraScale+ device device data sheets (see hp://www.xilinx.com/documentaon)
for successful CDR lock-to-data criteria.
After an RX Elastic Buffer Error
Aer an RX elasc buer overow or underow, a sequenal component reset targeng the RX
PCS must be triggered to ensure correct behavior.
After a PRBS Error
PRBSCNTRESET is asserted to reset the PRBS error counter.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 44
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English