Xilinx Virtex UltraScale+ FPGAs User Manual

The combinaon of CTLE, FFE, and DFE can compensate for both the pre-cursor and post-cursor
of the transmied bit. All equalizaon loops are auto-adapve to handle a wide range of channel
proles and to compensate for any PVT variaons.
Figure 39: GTM RX Equalization
Adaptation
Controller
CDR
Termination
P
N
AGC
ADC
FFE DFE
SIPO
CTLE
Data to PCS
X20924-053118
Ports and Attributes
The following table denes the RX equalizer ports.
Table 50: RX Equalizer Ports
Port Dir Clock Domain Description
CH[0/1]_RXADAPTRESET In Async This port is driven High and then deasserted
to start a single-mode reset on RX adaptation.
The reset is not dependent on RXRESETMODE
or RXPMARESETMASK setting.
CH[0/1]_RXADCCALRESET In Async Reserved. Tie to 1’b0.
CH[0/1]_RXADCCLKGENRESET In Async This port is driven High and then deasserted
to start a single-mode reset on the RX ADC
CLKGEN. The reset is not dependent on
RXRESETMODE or RXPMARESETMASK setting.
CH[0/1]_RXDFERESET In Async This port is driven High and then deasserted
to start a single-mode reset on the DFE. The
reset is not dependent on RXRESETMODE or
RXPMARESETMASK setting.
CH[0/1]_RXDSPRESET In Async This port is driven High and then deasserted
to start a single-mode reset on the DSP. The
reset is not dependent on RXRESETMODE or
RXPMARESETMASK setting.
CH[0/1]_RXEQTRAINING In Async Reserved. Tie to 1'b0.
The following table denes the RX equalizer aributes.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 88
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English