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Xilinx Virtex UltraScale+ FPGAs - Page 91

Xilinx Virtex UltraScale+ FPGAs
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Table 51: RX Equalizer Attributes (cont'd)
Attribute Type Description
CH[0/1]_RX_APT_CFG28A[15:0] 16-bit Adaptation loop override controls. Use the recommended
value from the Wizard.
Bit Description
[15:13] Reserved.
[12] Enable to override automatic gain control
(AGC) value according to attribute
CH[0/1]_RX_APT_CFG18A[11:6].
[11] Enable to override CTLE High frequency
loop (KH) value according to attribute
CH[0/1]_RX_APT_CFG18A[5:0].
[10] Enable to override CTLE Low frequency loop
(KL) value according to attribute
CH[0/1]_RX_APT_CFG17B[12:7].
[9] Enable to override Offset Cancelation (OS)
value according to attribute
CH[0/1]_RX_APT_CFG17B[6:0].
[8:5] Reserved.
[4] Enable to override FFE Tap HM4 value
according to attribute
CH[0/1]_RX_APT_CFG14B[5:0].
[3] Enable to override FFE Tap HM3 value
according to attribute
CH[0/1]_RX_APT_CFG14B[11:6].
[2] Enable to override FFE Tap HM2 value
according to attribute
CH[0/1]_RX_APT_CFG14A[7:0].
[1] Enable to override FFE Tap HM1 value
according to attribute
CH[0/1]_RX_APT_CFG14A[15:8].
[0] Adaptation override control. This bit must
be enabled to override the loops selected in
CH[0/1]_RX_APT_CFG28A, and
CH[0/1]_RX_APT_CFG28B. If this this bit is
set to low, all loops will be auto-adapting.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 91
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