Xilinx Virtex UltraScale+ FPGAs User Manual

Table 51: RX Equalizer Attributes (cont'd)
Attribute Type Description
CH[0/1]_RX_APT_CFG27B[15:0] 16-bit Adaptation loop freeze controls. Use the recommended
value from the Wizard.
Bit Description
[15:10] Reserved.
[9] Enable to freeze current FFE Tap HP11 adapt
value.
[8] Enable to freeze current FFE Tap HP10 adapt
value.
[7] Enable to freeze current FFE Tap HP9 adapt
value.
[6] Enable to freeze current FFE Tap HP8 adapt
value.
[5] Enable to freeze current FFE Tap HP7 adapt
value.
[4] Enable to freeze current FFE Tap HP6 adapt
value.
[3] Enable to freeze current FFE Tap HP5 adapt
value.
[2] Enable to freeze current FFE Tap HP4 adapt
value.
[1] Enable to freeze current FFE Tap HP3 adapt
value.
[0] Enable to freeze current FFE Tap HP2 adapt
value.
Note: Aribute CH[0/1]_RX_APT_CFG27A[0] must be
enabled to freeze the enabled loops in
CH[0/1]_RX_APT_CFG27B[15:0].
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 90
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English