1.1. V-Line = 100% VBaseLine and f-Line = 60.0 Hz
1.2. V-Bus = 100% VBaseBus and f-Bus = 60.15Hz
2. Check that a closing pulse is submitted at a closing angle equal to calculated phase
angle value from the formula below. Modern test sets will evaluate this
automatically.
Closing Angle = |( (f
Bus
– f
Line
) * tBreaker * 360 degrees) |
f
Bus
= Bus frequency
f
Line
= Line frequency
tBreaker = Set closing time of the breaker
3. Repeat with
3.1. V-Bus = 100% VBaseBus and f-bus = 60.25 Hz, to verify that the function does
not trip when frequency difference is above limit.
4. Verify that the closing command is not issued when the frequency difference is less
than the set value FreqDiffMin.
11.10.1.2 Testing the synchrocheck functionality
During the test of SESRSYN (25) for a single bay arrangement, these voltage inputs are
used:
V-Line
VA, VB or VC line 1 voltage input on the IED according to the connection in SMT
V-Bus V5 voltage input on the IED according to the connection in SMT
Testing the voltage difference
Set the voltage difference to 0.15 p.u. on the local HMI, and the test should check that
operation is achieved when the voltage difference VDiffSC is lower than 0.15 p.u.
The settings used in the test shall be final settings. The test shall be adapted to site setting
values instead of values in the example below.
Test with no voltage difference between the inputs.
Test with a voltage difference higher than the set VDiffSC.
1MRK 504 165-UUS - Section 11
Testing functionality by secondary injection
Transformer protection RET670 2.2 ANSI 239
Commissioning manual
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