1. Inject the polarizing voltage 3V0 at 5% of VBase (EF4PTOC, 51N67N) where the
current is lagging the voltage by 65°.
2. Inject current (65° lagging the voltage) in one phase at about 110% of the set
operating current, and switch the current off with the switch.
3. Switch the fault current on and measure the operating time of the communication
logic.
Use the TRIP signal from the configured binary output to stop the timer.
4. Compare the measured time with the set value tCoord.
5. Activate the CR binary input.
6. Check that the CRL output is activated when the CR input is activated.
7. Switch the fault current on (110% of the set operating current) and wait longer than
the set value tCoord.
No TRIP signal should appear.
8. Switch the fault current off.
9. Reset the CR binary input.
10. Activate the BLOCK digital input.
11. Switch the fault current on (110% of the set operating current) and wait for a period
longer than the set value tCoord.
No TRIP signal should appear.
12. Switch the fault current and the polarizing voltage off.
13. Reset the BLOCK digital input.
Permissive scheme
1. Inject the polarizing voltage 3V0, which is 5% of VBase (EF4PTOC, 51N67N)
where the current is lagging the voltage by 65°.
2. Inject current (65° lagging the voltage) into one phase at about 110% of the set
operating current, and switch the current off with the switch.
3. Switch the fault current on, (110% of the set operating current) and wait longer than
the set value tCoord.
No TRIP signal should appear, and the CS binary output should be
activated.
4. Switch the fault current off.
5. Activate the CR binary input.
Section 11 1MRK 504 165-UUS -
Testing functionality by secondary injection
266 Transformer protection RET670 2.2 ANSI
Commissioning manual
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