Chapter 7 217
Digital Signal Interface Module
Clock Timing
The levels will degrade above the warranted level clock rates, but they may still be usable.
Serial Port Configuration Clock Rates
For a serial port configuration, the lower clock rate limit is determined by the word size (word size and
sample size are synonymous), while the maximum clock rate limit remains constant at 150 MHz for LVTTL
and CMOS logic types, and 400 MHz for an LVDS logic type.
The reverse is true for the sample rate. The lower sample (word) rate value of 1 kHz remains while the upper
limit of the sample rate varies with the word size. For example, a five-bit sample for an LVTTL or CMOS
logic type yields the following values in serial mode:
• Clock rate of 5 kHz through 150 MHz
• Sample rate of 1 kHz through 30 MHz
Refer to Table 7-3 and Table 7-4, for the serial clock rates.
Table 7-1 Warranted Parallel Output Level Clock Rates and Maximum
Clock Rates
Logic Type
Warranted Level Clock Rates Maximum Clock Rates (typical)
IQ Signal Type
IF Signal Type
1
1. The IF signal type is not available for a serial port configuration.
IQ Signal Type IF Signal Type
LVTTL and CMOS 100 MHz 100 MHz 150 MHz 150 MHz
LVDS 200 MHz 400 MHz 400 MHz 400 MHz
Table 7-2 Warranted Parallel Input Level Clock Rates and Maximum Clock
Rates
Logic Type Warranted Level Clock Rates Maximum Clock Rates (typical)
LVTTL and CMOS 100 MHz 100 MHz
LVDS 100 MHz 400 MHz
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