218 Chapter 7
Digital Signal Interface Module
Clock Timing
Parallel and Parallel Interleaved Port Configuration Clock Rates
Parallel and parallel interleaved port configurations have other limiting factors for the clock and sample
rates:
• logic type
• Clocks per sample selection
• IQ or IF digital signal type
Clocks per sample (clocks/sample) is the ratio of the clock to sample rate. For an IQ signal type, the sample
rate is reduced by the clocks per sample value when the value is greater than one. For an IF signal or an input
signal, clocks per sample is always set to one. Refer to Table 7-5 for the Output mode parallel and parallel
interleaved port configuration clock rates.
Table 7-3 Output Serial Clock Rates
Logic Type Minimum Rate Maximum Rate
LVDS 1 x (word size) kHz 400 MHz
LVTTL and CMOS 1 x (word size) kHz 150 MHz
Table 7-4 Input Serial Clock Rates
Logic Type Data Type Minimum Rate Maximum Rate
LVDS Samples 1 x (word size) kHz 400
Pre-FIR
Samples
1 x (word size) kHz
the smaller of: 50
1
x (word size) MHz
or
400 MHz
1. The maximum sample rate depends on the selected filter when the data rate is Pre-FIR Samples. Refer to “Input Mode” on page
232 for more information.
LVTTL and CMOS N/A 1 x (word size) kHz 150 MHz
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