Chapter 14 High-Speed Counter (HSC) instructions
340 Rockwell Automation Publication 2080-RM001D-EN-E - February 2015
The MV bit is controlled by the user program and retains its value through a
power cycle. The user program must set and clear the MV bit.
Underflow Mask (HSC0.MN)
Parameter Data format HSC modes User program access
HSCO.MN bit 2...9 read only
The MN (Underflow Mask) control bit is used to enable (allow) or disable (not
allow) an underflow interrupt from occurring. If the bit is clear (0), and an
Underflow Reached condition is detected by the HSC, the HSC user interrupt is
not executed.
The MN bit is controlled by the user program and retains its value through a
power cycle. The user program must set and clear the MN bit.
High Preset Mask (HSC0.MH)
Parameter Data format HSC modes User program access
HSCO.MH bit 0...9 read only
The MH (High Preset Mask) control bit is used to enable (allow) or disable (not
allow) a high preset interrupt from occurring. If this bit is clear (0), and a High
Preset Reached condition is detected by the HSC, the HSC user interrupt is not
executed.
The MH bit is controlled by the user program and retains its value through a
power cycle. The user program must set and clear the MH bit.
Low Preset Mask (HSC0.ML)
Parameter Data format HSC modes User program access
HSCO.ML bit 2...9 read only
The ML (Low Preset Mask) control bit is used to enable (allow) or disable (not
allow) a low preset interrupt from occurring. If this bit is clear (0), and a Low
Preset Reached condition is detected by the HSC, the HSC user interrupt is not
executed.
The ML bit is controlled by the user program and retains its value through a
power cycle. The user program must set and clear the ML bit.
To Next Page
Loading...
