Altera DE1-SoC - Page 63

DE1-SoC User Manual
62
www.terasic.com
March 14, 2014
Figure 5-2 Buttons and switches for the audio recorder and player
Figure 5-3 shows the block diagram of audio recorder and player design. There are hardware and
software parts in the block diagram. The software part stores the Nios II program in the on-chip
memory. The software part is built under Eclipse in C programming language. The hardware part is
built under Qsys in Quartus II. The hardware part includes all the other blocks such as the “AUDIO
Controller”, which is a user-defined Qsys component and it is designed to send audio data to the
audio chip or receive audio data from the audio chip.
The audio chip is programmed through I2C protocol, which is implemented in C code. The I2C pins
from the audio chip are connected to Qsys system interconnect fabric through PIO controllers. The
audio chip is configured in master mode in this demonstration. The audio interface is configured as
16-bit I2S mode. 18.432MHz clock generated by the PLL is connected to the MCLK/XTI pin of the
audio chip through the audio controller.
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