Altera DE1-SoC - Page 73

DE1-SoC User Manual
72
www.terasic.com
March 14, 2014
de-interlacing operation. The VGA Controller also generates data request and odd/even selection
signals to the SDRAM Frame Buffer and filed selection multiplexer (MUX). The YUV422 to
YUV444 block converts the selected YcrCb 4:2:2 (YUV 4:2:2) video data to the YcrCb 4:4:4 (YUV
4:4:4) video data format.
Finally, the YcrCb_to_RGB block converts the YcrCb data into RGB data output. The VGA
Controller block generates standard VGA synchronous signals VGA_HS and VGA_VS to enable
the display on a VGA monitor.
Figure 5-9 Block diagram of the TV box demonstration
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 Project directory: DE1_SoC_TV
 Bitstream used: DE1_SoC_TV.sof
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Demo batch directory: \DE1_SoC_TV \demo_batch
The folder includes the following files:
 Batch file: DE1_SoC_TV.bat
 FPGA configuration file : DE1_SoC_TV.sof
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