REG:2F:04 – EVC_PHE – PHR Error Counter
The fields of the EVC_PHE register are described below:
Description of fields within Sub-Register 0x2F:04 – PHR Error Counter
EVC_PHE
reg:2F:04
bits:11–0
PHR Error Event Counter. The EVC_PHE field is a 12-bit counter of PHY Header Errors. This
counts the reporting of RXPHE error events in Register file: 0x0F – System Event Status
Register.
NB: For this counter to be active, counting needs to be enabled by the setting the EVC_EN bit
in Sub-Register 0x2F:00 – Event Counter Control.
The remaining bits of this register are reserved.
7.2.48.3 Sub-Register 0x2F:06 – RSD Error Counter
Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x06 is the RSD Error event counter.
REG:2F:06 – EVC_RSE – RSD Error Counter
The fields of the EVC_RSE register are described below:
Description of fields within Sub-Register 0x2F:06 – RSD Error Counter
EVC_RSE
reg:2F:06
bits:11–0
Reed Solomon decoder (Frame Sync Loss) Error Event Counter. The EVC_RSE field is a 12-bit
counter of the non-correctable error events that can occur during Reed Solomon decoding.
This counts the reporting of RXRFSL error events in Register file: 0x0F – System Event Status
Register.
NB: For this counter to be active, counting needs to be enabled by the setting the EVC_EN bit
in Sub-Register 0x2F:00 – Event Counter Control.
The remaining bits of this register are reserved.
7.2.48.4 Sub-Register 0x2F:08 – FCS Good Counter
Frame Check Sequence Good Event Counter
Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x08 is the FCS good event counter.
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