I1
,
I
I
I
I
I
3
8
100
MHz
CLOCK
11
i~
I
I
I
I
I
I
I
I
I1
I
I I
I
I
;
J
I1
I
I
I
I I
I>
I
I
U5 PIN
1
I
I
I1
:
I
I
I I
I1
I
,
,
.
-.
I
I
I
I
I
I
1
I
I
I I
I1
I'
I
I
I
I
I
;
U7 PIN
4
I I I
I
I
I
I
I1
I1
1
I
I
I
I
I
I
I
I I I
I
I
I
I I
I
I
I
I
I:
I
I
'----+'I
:
I
I
I
I
I
I
I
U8 PIN
2
(GATE)
Figure 107-1. Gate Generator Timing Diagram
BAND
3
AMPLITUDE DETERMINATION
This circuit consists of three main parts.
THE POWER METER ZERO DAC
is
used to automatically zero offsets in the Power Meter. It
consists of two 8 bit latching DACs
(U3, U4), and a comparator (U14A). All the latching DACs are
driven in parallel by shift register U16, with the appropriate DAC being written to by the four write
lines
(U15, pins
2,
4,
6,
8). The coarse DAC (U3) has a range of
2
200 micro amps, and the fine
DAC (U4) has a range of
+1.5 micro amps. The Power Meter Zero DAC (U3) is adjusted so that
on step 1
U14A
is
not set, but on the next step U14A is set. This adjusts the input to U14 to Ovolts,
nulling any offsets in the power meter circuit.
THE POWER METER consists of a
15
dB switchable gain stage (U9), an
8
bit DACpsed as a variable
attenuator
(UlO), a 100 mV comparator (U14B). and a latch (half of U17). Two variable attenuators
are used, on counters equipped with the option 02 power meter, to provide greater resolution
(U10,
U12).
When the detected signal from the microwave converter enters U9 the power meter
is
first set for
maximum gain and minimum attenuation. Next the latch
(U17) is reset. If the input to the compara-
tor
(U14B) is greater than 100mV, latch U17 will be set. The signal amplitude to the comparator
is
then reduced, and the process is repeated until latch U17 no longer gets set. The input amplitude
can then be calculated from the switch and DAC settings. On counters without the power meter
option the amplitude
is
calculated to a 3dB resolution. On counters with the power meter option
the amplitude
is
calculated to
a
resolution of O.1dB.
Scans by ArtekMedia © 2007
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