43B
Service Manual
3-24
Amplifier 3 and 4 and connected resistors supply the REFADCT and REFADCB
reference voltages for the ADC’s. Both voltages directly influence the gain accuracy of
the ADC’s.
The T-ASIC can select some of the reference voltages to be output to pin 8 (REFATT).
The REFATT voltage is used for internal calibration of the Input 1 and B overall gain.
Tracerot Signal
The T-ASIC generates the TRACEROT signal, used by the C-ASIC’s. Control signals
TROTRST and TROTCLK are provided by the D-ASIC.
AC/DC Relay and Ω
ΩΩ
Ω/F Relay Control
The Input 1/2 AC/DC relays K171/K271, and the Input 1 Ω/F relay K173 are controlled
by the T-ASIC output signals ACDCA (pin 22), ACDCB (pin 23) and OHMA (pin 24).
SCLK, SDAT Signals
T-ASIC control data, e.g. for trigger source/mode/edge selection and relay control, are
provided by the D-ASIC via the SCLK and SDAT serial control lines..
3.3.4 Digital Circuit
See the Fluke 43B block diagram Figure 3-1, and circuit diagram Figure 9-4.
The Digital part is built up around the D-ASIC MOT0002. It provides the following
functions:
• Analog to Digital Conversion of the conditioned Input 1 and Input 2 signals
• ADC data acquisition for traces and numerical readings
• Trigger processing
• Pulse width measurements, e.g. for capacitance measurement function
• Microprocessor, Flash EPROM and RAM control
• Display control
• Keyboard control, ON/OFF control
• Miscellaneous functions, as PWM signal generation, SDA-SCL serial data control,
Slow ADC control, serial RS232 interface control, buzzer control, etcetera.
The D-ASIC is permanently powered by the +3V3GAR voltage. The P-ASIC indicates
the status of the +3V3GAR voltage via the VGARVAL line connected to D-ASIC pin
89. If +3V3GAR is correct VGARVAL is high, the D-ASIC will start-up, and the
D-ASIC functions are operative regardless of the test tool is ON/OFF status.
Analog to Digital Conversion
For voltage and resistance measurements, the Input 1/2 (2 for voltage only) signal is
conditioned by the C-ASIC to 150 mV/d. Zero and gain measurements are done to
eliminate offset and gain errors. The C-ASIC output voltage is supplied to the Input 1/2
ADC (D401/D451 pin 5). The ADC samples the analog voltage, and converts it into an
8-bit data byte (D0-D7). The data are read and processed by the D-ASIC, see below
“ADC data Acquisition”.
The sample rate depends on the sample clock supplied to pin 24. The sample rate is 5
MHz or 25 MHz, depending on the instrument mode. The ADC input signal is sampled
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