43B
Service Manual
3-26
The circuit D480 and related parts create a delay for the ROMWRITE enable signal.
This prevents the ROM write proces being disabled before all data have been written
(PCB version 3 up only).
Display Control
The LCD unit includes the LCD, the LCD drivers, and the fluorescent back light lamp.
It is connected to the main board via connector X453. The LCD is built up of 240
columns of 240 pixels each (240x240 matrix). The D-ASIC supplies the data and
control signals for the LCD drivers on the LCD unit (Figure 3-13).
X1..80 X81..160 X161..240
Y1..80
Y81..160
Y161..240
LCD
Common Driver Common Driver Common Driver
LCDAT0-3
DATACLK0
FRAME
Din
Din
Din
DCl
LINECLK
LnCl
LnCl
DCl
LnCl
DCl
MM
M
M
MMM
LnCl
Do Di Do
Di
Carry
Carry
FRONTVIEW
PIXEL (0,0)
TOP
LEFT
Column
Driver
Column
Driver
Column
Driver
LnCl LnCl
Figure 3-13. LCD Control
Each 14 ms the LCD picture is refreshed during a frame. The frame pulse (FRAME)
indicates that the concurrent LINECLK pulse is for the first column. The column drivers
must have been filled with data for the first column. Data nibbles (4 bit) are supplied via
lines LCDAT0-LCDAT3. During 20 data clock pulses (DATACLK0) the driver for
Y161..240 is filled. When it is full, it generates a carry to enable the driver above it,
which is filled now. When a column is full, the LINECLK signal transfers the data to the
column driver outputs. Via the common drivers the LINECLK also selects the next
column to be filled. So after 240 column clocks a full screen image is built up.
The LCD unit generates various voltage levels for the LCD drivers outputs to drive the
LCD. The various levels are supplied to the driver outputs, depending on the supplied
data and the M(ultiplex) signal. The M signal (back plane modulation) is used by the
LCD drivers to supply the various DC voltages in such an order, that the average voltage
does not contain a DC component. A DC component in the LCD drive voltage may
cause memory effects in the LCD.
The LCD contrast is controlled by the CONTRAST voltage. This voltage is controlled
by the D-ASIC, which supplies a PWM signal (pin 37 CONTR-D) to PWM filter
R436/C436. The voltage REFPWM1 is used as bias voltage for the contrast adjustment
circuit on the LCD unit. To compensate for contrast variations due to temperature
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