Furuno FELCOM 15 - Page 146

AP1.3 Channel types and Signal processing
AP1-23
Scrambling
Scrambling prevents 0 or 1 from continuing excessively; if 0 or 1 continues, clock
recovery would be reduced at the BPSK modulator. For scrambling, the output is
gained by inputting to the output from the scramble generator and the modulo-2 adder
(exclusive OR).
Fig. AP1.3.6 Scrambling
Convolutional Encoding
The convolutional encoding is a method that the receiving side controls to decrease the
random error occurred at the communication path so that the redundancy bit is added
to the data bit. The convolutional encoder used by the Inmarsat C consists of the 7 bits
shift register (constraint length-7) and two modulo-2 adderes (exclusive OR). The
scrambled bit string is output as the half-rate coded symbols.
Fig. AP1.3.7 Encoding
LSB MSB
+
X0 X1
X2 X3 X4 X5 X6 X7
+
Data
G
DATA
OUT
G=X3+X4+X5+X7
Start state
:
1000000
(To encoder)
Modulo-2 adder
(exclusive OR)
Scramblin
g
Generator
(Shift Register)
X0 X1 X2 X3 X4 X5 X6
G1=X0+X2+X3+X5 + X6
Start state
:
0 0 0 0 0 0
Coded symbols
(To interleaver)
exclusive OR
Formatted
(Scrambled) data
G2=X0+X1+X2+X3 + X6
G2
G1
+
+
(Half-rate: Output of 2 bits
with input of 1 bit)
exclusive OR