5.3 Status monitor
5-12
Rx AGC Level
The BPSK modulated I signal and Q signal at RF CON/CPU board is input to U14
(CPU) to output C/N data. RF CON/CPU board outputs the AGC voltage (Reverse
AGC) based on the I signal and Q signal. The circuit to be controlled is the pin diodes
of CR31 and CR32. “OK” appears when the level is more than 60.
When the value is near 255, the receiving signal is not input to RF CON/CPU board
from the antenna unit.
The followings are the parts which the error may be occurred;
- Antenna unit
- RF CON/CPU board.
REF Offset Freq.
The error rate is increased when the RX frequency from the satellite differs from the
carrier frequency input to the mixing circuit. This is the correction value of the carrier
frequency input to mixing circuit. RF CON/CPU board detects the frequency difference
to the RX frequency and the phase difference between I signal and Q signal. These data
are fed back as DDS data. DDS output is the reference frequency of the PLL synthesizer
circuit. PLL synthesizer output frequency is changed by controlling this frequency to
match to the RX frequency.
“OK” appears when the Offset Freq. is less than 150 Hz.
Synthe Local
RF CON/CPU board monitors the PLL unlock signal, U20 of the PLL synthesizer
circuit. The error may be occurred;
- RF CON/CPU board.
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