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Appendix B -Settings and Signals

P446SV

B208

P446SV-TM-EN-1

Main Page

Default Chapter3
- Table of Contents3
Chapter 1 Introduction33
- Figure 197: Circuit Breaker Fail Logic - Part33
- Circuit Breaker Fail Logic - Part34
- Aided Scheme34
- Rear Serial Port34
- Figure 198: Circuit Breaker Fail Logic - Part34
- Figure 250: TCS Scheme34
Chapter Overview35
- Circuit Breaker Fail Logic - Part35
- Cip35
- Figure 199: Circuit Breaker Fail Logic - Part35
Foreword36
- Target Audience36
- Typographical Conventions36
- Cip36
- Nomenclature37
- Compliance37
- Cip37
Product Scope38
- Product Versions38
- Cip38
- Ordering Options39
- Figure 1: P40L Family - Version Evolution39
- Figure 145: Autoreclose System Map - Part39
Features and Functions40
- Distance Protection Functions40
- Protection Functions40
- Figure 146: Autoreclose System Map - Part40
- Control Functions41
- Measurement Functions41
- Communication Functions41
- Figure 147: Autoreclose System Map - Part41
Logic Diagrams43
- Figure 2: Key to Logic Diagrams44
Functional Overview45
- Figure 3: Functional Overview45
Chapter 2 Safety Information47
Chapter Overview49
Health and Safety50
Symbols51
Installation, Commissioning and Servicing52
- Lifting Hazards52
- Electrical Hazards52
- UL/CSA/CUL Requirements53
- Fusing Requirements53
- Equipment Connections54
- Protection Class 1 Equipment Requirements54
- Pre-Energisation Checklist55
- Peripheral Circuitry55
- Upgrading/Servicing56
Decommissioning and Disposal57
Regulatory Compliance58
- EMC Compliance: 2014/30/EU58
- LVD Compliance: 2014/35/EU58
- R&TTE Compliance: 2014/53/EU58
- UL/CUL Compliance58
- ATEX Compliance: 2014/34/EU58
Chapter 3 Hardware Design61
Chapter Overview63
Hardware Architecture64
- Figure 4: Hardware Architecture64
Mechanical Implementation65
- Housing Variants65
- Figure 5: Exploded View of IED65
- List of Boards66
Front Panel67
- 40TE Front Panel67
- Front Panel Compartments67
- Figure 6: Front Panel (40TE)67
- Keypad68
- Front Serial Port (SK1)68
- Front Parallel Port (SK2)69
- Fixed Function Leds69
- Programable Leds69
Rear Panel70
- Figure 7: Rear View of Populated Case70
Boards and Modules71
- Pcbs71
- Figure 8: Rear Connection to Terminal Block71
- Main Processor Board72
- Figure 9: Main Processor Board72
- Power Supply Board73
- Figure 10: Power Supply Board73
- Figure 11: Power Supply Assembly74
- Watchdog75
- Figure 12: Power Supply Terminals75
- Rear Serial Port76
- Figure 13: Watchdog Contact Terminals76
- Figure 14: Rear Serial Port Terminals77
- Figure 15: IEC 61850-9-2LE Board77
- IEC61850-9-2LE Ethernet Board77
- Standard Output Relay Board78
- Figure 16: Standard Output Relay Board - 8 Contacts78
- IRIG-B Board79
- Figure 17: IRIG-B Board79
- Fibre Optic Board80
- Figure 18: Fibre Optic Board80
- Rear Communication Board81
- Ethernet Board81
- Figure 19: Rear Communication Board81
- Figure 20: Ethernet Board81
- Redundant Ethernet Board83
- Figure 21: Redundant Ethernet Board83
- Coprocessor Board85
- Coprocessor Board with 1PPS Input85
- Figure 22: Fully Populated Coprocessor Board85
- High Break Output Relay Board86
- Figure 23: High Break Relay Output Board86
- Figure 24: High Break Contact Operation87
Chapter 4 Software Design89
Chapter Overview91
Sofware Design Overview92
- Figure 25: Software Architecture92
System Level Software93
- Real Time Operating System93
- System Services Software93
- Self-Diagnostic Software93
- Startup Self-Testing93
- System Boot93
- System Level Software Initialisation94
- Platform Software Initialisation and Monitoring94
- Continuous Self-Testing94
Platform Software96
- Record Logging96
- Settings Database96
- Interfaces96
Protection and Control Functions97
- Acquisition of Samples97
- Frequency Tracking97
- Direct Use of Sample Values97
- Distance Protection97
- Fourier Signal Processing98
- Figure 26: Frequency Response of FIR Filters98
- Programmable Scheme Logic99
- Event Recording99
- Figure 27: Frequency Response (Indicative Only)99
- Disturbance Recorder100
- Fault Locator100
- Function Key Interface100
Chapter 5 Configuration101
Chapter Overview103
Settings Application Software104
Using the HMI Panel105
- Navigating the HMI Panel106
- Getting Started106
- Figure 28: Navigating the HMI106
- Default Display107
- Default Display Navigation108
- Figure 29: Default Display Navigation108
- Password Entry109
- Processing Alarms and Records110
- Menu Structure110
- Changing the Settings111
- Direct Access (the Hotkey Menu)112
- Setting Group Selection Using Hotkeys112
- Control Inputs113
- Circuit Breaker Control113
- Function Keys114
Line Parameters116
- Tripping Mode116
- CB Trip Conversion Logic Diagram117
- Residual Compensation117
- Figure 30: Circuit Breaker Trip Conversion Logic Diagram (Module 63)117
- Mutual Compensation118
Date and Time Configuration120
- Using an SNTP Signal120
- Using an IRIG-B Signal120
- Using an IEEE 1588 PTP Signal120
- Without a Timing Source Signal121
- Time Zone Compensation121
- Daylight Saving Time Compensation122
Settings Group Selection123
Chapter 6 Sampled Value Operation125
Chapter Overview127
Introduction to Sampled Values128
- Figure 31: Comparison of Conventional IED and Sampled Values IED128
Data Resampling129
- Figure 32: Data Sampling Using an IEC 61850-9-2LE Interface129
Sampled Value Alignment130
- Channel Mappings for SAV Test, SAV Questionable, SAV Invalid130
- Data Quality130
- Impact of Data Quality on Protection Functions131
- Process Bus Performance131
- Sample Loss Data132
- VT Switching132
- Virtual Inputs and Outputs133
- P446, P546, P841B Virtual Inputs and Outputs Ddbs133
- Virtual CT and VT Ratio Settings133
- IED Alarms134
- P446, P546, P841B Alarms134
- Distance Protection137
Chapter 7 Distance Protection137
Chapter Overview139
Introduction140
- Distance Protection Principle140
- Performance Influencing Factors140
- Figure 33: System Impedance Ratio140
- Impedance Calculation141
- Implementation with Comparators141
- Polarization of Distance Characteristics141
Distance Measuring Zones Operating Principles142
- Mho Characteristics143
- Directional Mho Characteristic for Phase Faults143
- Offset Mho Characteristic for Phase Faults143
- Figure 34: Directional Mho Element Construction143
- Directional Self-Polarized Mho Characteristic for Earth Faults144
- Figure 35: Offset Mho Characteristic144
- Figure 36: Directional Mho Element Construction - Impedance Domain145
- Offset Mho Characteristic for Earth Faults146
- Figure 37: Offset Mho Characteristics - Impedance Domain146
- Figure 38: Offset Mho Characteristics - Voltage Domain147
- Memory Polarization of Mho Characteristics148
- Dynamic Mho Expansion and Contraction148
- Figure 39: Simplified Forward Fault148
- Figure 40: Mho Expansion - Forward Fault149
- Figure 41: Simplified Reverse Fault150
- Cross Polarization of Mho Characteristics151
- Figure 42: Mho Contraction - Reverse Fault151
- Implementation of Mho Polarization152
- Quadrilateral Characteristic153
- Figure 43: Simplified Quadrilateral Characteristics153
- Directional Quadrilaterals154
- Figure 44: General Quadrilateral Characteristic Limits154
- Figure 45: Directional Quadrilateral Characteristic155
- Figure 46: Quadrilateral Characteristic Featuring 2 Directional Forward Zones and 1 Offset Zone155
- Figure 47: Five-Sided Polygon Formed by Quadrilateral Characteristic with Directional-Line156
- Quadrilateral Characteristic for Phase Faults158
- Figure 48: Impedance Reach Line Construction158
- Figure 49: Reverse Impedance Reach Line Construction159
- Figure 50: Resistive Reach of Phase Elements160
- Figure 51: Resistive Reach Line Construction160
- Figure 52: Reverse Resistive Reach Line Construction161
- Figure 53: Phase Fault Quadrilateral Characteristic Summary161
- Earth Fault Quadrilateral Characteristics162
- Figure 54: Impedance Reach Line in Z1 Plane164
- Figure 55: Impedance Reach Line in ZLP Plane165
- Figure 56: General Characteristic in ZLP Plane166
- Figure 57: Phase Relations between I2 and Iph for Leading and Lagging Polarizing Currents167
- Figure 58: General Characteristic in Z1 Plane168
- Figure 59: Simplified Characteristic in Z1 Plane169
Phase and Earth Fault Distance Protection Implementation171
- Phase Fault Characteristics171
- Earth Fault Characteristics171
- Distance Protection Tripping Decision171
- Distance Protection Phase Selection172
- Faulted Phase Selection172
- Biased Neutral Current Detector173
- Figure 60: Phase to Phase Current Changes for C Phase-To-Ground (CN) Fault173
- Distance Element Zone Settings174
- Directionalizing the Distance Elements174
- Figure 61: Biased Neutral Current Detector Characteristic174
- Advanced Distance Zone Settings175
- Distance Zone Sensitivities175
- Capacitor VT Applications176
- Cvts with Passive Suppression of Ferroresonance176
- Cvts with Active Suppression of Ferroresonance176
- Load Blinding177
- Figure 62: Load Blinder Characteristics177
- Cross Country Fault Protection178
Delta Directional Element179
- Delta Directional Principle and Setup179
- Delta Directional Decision180
- Figure 63: Sequence Networks Connection for an Internal A-N Fault180
- Figure 64: - DV Forward and Reverse Tripping Regions181
Application Notes182
- Setting Mode Choice182
- Operating Characteristic Selection182
- Phase Characteristic182
- Figure 65: Settings Required to Apply a Quadrilateral Zone182
- Earth Fault Characteristic183
- Zone Reach Setting Guidelines183
- Figure 66: Settings Required to Apply a Mho Zone183
- Quadrilateral Resistive Reaches184
- Earth Fault Resistive Reaches and Tilting184
- Dynamic Tilting185
- Figure 67: Over-Tilting Effect185
- Fixed Tilting186
- Phase Fault Zone Settings186
- Directional Element for Distance Protection187
- Filtering Setup187
- Distance Digital Filter187
- Setting up Cvts187
- Load Blinding Setup188
- Polarizing Setup188
- Delta Directional Element Setting Guidelines189
- Delta Thresholds189
- Distance Protection Worked Example189
- Line Impedance Calculation190
- Figure 68: Example Power System190
- Residual Compensation for Earth Fault Elements191
- Zone 1 Phase and Ground Reach Settings191
- Zone 2 Phase and Ground Reach Settings191
- Zone 3 Phase and Ground Reach Settings192
- Zone 3 Reverse Reach Settings192
- Zone 4 Reverse Reach Settings192
- Load Avoidance193
- Quadrilateral Resistive Reach Settings193
- Teed Feeder Applications194
- Figure 69: Apparent Impedances Seen by Distance Protection on a Teed Feeder195
Chapter 8 Carrier Aided Schemes197
Chapter Overview199
Introduction200
Carrier Aided Schemes Implementation201
- Carrier Aided Scheme Types201
- Figure 70: Scheme Assignment201
- Default Carrier Aided Schemes202
Aided Distance Scheme Logic203
- Permissive Underreach Scheme203
- Permissive Over-Reach Scheme204
- Figure 71: Aided Distance PUR Scheme204
- Permissive Overreach Trip Reinforcement206
- Figure 72: Aided Distance por Scheme206
- Permissive Overreach Weak Infeed Features207
- Permissive Scheme Loss of Guard207
- Current Reversal Guard Logic208
- Figure 73: Example of Fault Current Reversal of Direction208
- Aided Distance Blocking Schemes209
- Aided Distance Unblocking Schemes210
- Figure 74: Aided Distance Blocking Scheme (BOP)210
- Aided Distance Logic Diagrams212
- Aided Distance Send Logic212
- Carrier Aided Schemes Receive Logic212
- Figure 75: Aided Distance Send Logic212
- Aided Distance Tripping Logic213
- PUR Aided Tripping Logic213
- Figure 77: Aided Distance Tripping Logic213
- Figure 78: PUR Aided Tripping Logic213
- POR Aided Tripping Logic214
- Aided Scheme Blocking 1 Tripping Logic215
- Aided Scheme Blocking 2 Tripping Logic215
- Figure 79: por Aided Tripping Logic215
Aided DEF Scheme Logic216
- Aided DEF Introduction216
- Implementation216
- Aided DEF Polarization216
- Zero Sequence Polarizing217
- Negative Sequence Polarizing218
- Figure 82: Virtual Current Polarization218
- Aided DEF Setting Guidelines219
- Figure 83: Directional Criteria for Residual Voltage Polarization219
- Aided DEF por Scheme220
- Aided DEF Blocking Scheme221
- Figure 84: Aided DEF por Scheme221
- Aided DEF Logic Diagrams222
- DEF Directional Signals222
- Figure 85: Aided DEF Blocking Scheme222
- Figure 86: DEF Directional Signals222
- Aided DEF Send Logic223
- Carrier Aided Schemes Receive Logic223
- Figure 76: Carrier Aided Schemes Receive Logic223
- Figure 87: Aided DEF Send Logic223
- Figure 88: Carrier Aided Schemes Receive Logic223
- Aided DEF Tripping Logic224
- Figure 89: Aided DEF Tripping Logic224
- POR Aided Tripping Logic225
- Aided Scheme Blocking 1 Tripping Logic226
- Aided Scheme Blocking 2 Tripping Logic226
- Figure 80: Aided Scheme Blocking 1 Tripping Logic226
- Figure 81: Aided Scheme Blocking 2 Tripping Logic226
- Figure 90: por Aided Tripping Logic226
- Figure 91: Aided Scheme Blocking 1 Tripping Logic226
- Figure 92: Aided Scheme Blocking 2 Tripping Logic226
Aided Delta Scheme Logic227
- Aided Delta por Scheme227
- Aided Delta Blocking Scheme228
- Figure 93: Aided Delta por Scheme228
- Figure 94: Aided Delta Blocking Scheme229
- Aided Delta Logic Diagrams230
- Aided Delta Send Logic230
- Carrier Aided Schemes Receive Logic230
- Figure 95: Aided Delta Send Logic230
- Figure 96: Carrier Aided Schemes Receive Logic230
- Aided Delta Tripping Logic231
- Figure 97: Aided Delta Tripping Logic231
- POR Aided Tripping Logic232
- Aided Scheme Blocking 1 Tripping Logic233
- Aided Scheme Blocking 2 Tripping Logic233
- Figure 98: por Aided Tripping Logic233
- Figure 99: Aided Scheme Blocking 1 Tripping Logic233
- Figure 100: Aided Scheme Blocking 2 Tripping Logic233
Application Notes234
- Aided Distance PUR Scheme234
- Aided Distance por Scheme234
- Aided Distance Blocking Scheme234
- Aided DEF por Scheme235
- Aided DEF Blocking Scheme235
- Aided Delta por Scheme235
- Aided Delta Blocking Scheme235
- Teed Feeder Applications236
- Figure 101: Apparent Impedances Seen by Distance Protection on a Teed Feeder236
- POR Schemes for Teed Feeders237
- PUR Schemes for Teed Feeders237
- Blocking Schemes for Teed Feeders238
- Figure 102: Problematic Fault Scenarios for PUR Scheme Application to Teed Feeders238
Chapter 9 Non-Aided Schemes241
Chapter Overview243
Non-Aided Schemes244
Basic Schemes245
- Basic Scheme Modes245
- Figure 103: any Distance Start246
- Figure 104: Standard Basic Scheme Mode Logic246
- Basic Scheme Setting247
- Figure 105: Alternative Basic Timer Start Scheme Mode Logic247
- Figure 106: Basic Time Stepped Distance Scheme248
Trip on Close Schemes249
- Figure 107: Trip on Close Logic249
- Switch on to Fault (SOTF)250
- Switch Onto Fault Mode250
- Figure 108: Trip on Close Based on CNV Level Detectors250
- SOTF Tripping251
- SOTF Tripping with CNV251
- Trip on Reclose (TOR)251
- Figure 109: SOTF Tripping251
- Figure 110: SOTF Tripping with CNV251
- Trip on Reclose Mode252
- TOR Tripping Logic for Appropriate Zones252
- TOR Tripping Logic with CNV252
- Polarisation During Circuit Engergisation252
- Figure 111: TOR Tripping Logic for Appropriate Zones252
- Figure 112: TOR Tripping Logic with CNV252
Zone1 Extension Scheme253
- Figure 113: Zone 1 Extension Scheme253
- Figure 114: Zone 1 Extension Logic253
Loss of Load Scheme254
- Figure 115: Loss of Load Accelerated Trip Scheme254
- Figure 116: Loss of Load Logic255
Chapter 10 Power Swing Functions257
Chapter Overview259
Introduction to Power Swing Blocking260
- Figure 117: Power Transfer Related to Angular Difference between Two Generation Sources260
Power Swing Blocking262
- Power Swing Detection262
- Settings-Free Power Swing Detection262
- Figure 118: Phase Selector Timing for Power Swing Condition263
- Figure 119: Phase Selector Timing for Fault Condition263
- Slow Power Swing Detection264
- Figure 120: Phase Selector Timing for Fault During a Power Swing264
- Figure 121: Slow Power Swing Detection Characteristic265
- Detection of a Fault During a Power Swing266
- Power Swing Blocking Configuration266
- Power Swing Load Blinding Boundary267
- Power Swing Blocking Logic268
- Figure 122: Load Blinder Boundary Conditions268
- Power Swing Blocking Setting Guidelines269
- Figure 123: Power Swing Blocking Logic269
- Setting the Resistive Limits270
- Setting the Reactive Limits270
- Figure 124: Setting the Resistive Reaches270
- PSB Timer Setting Guidelines271
- Figure 125: Reactive Reach Settings271
- Figure 126: PSB Timer Setting Guidelines272
Out of Step Protection273
- Out of Step Detection273
- Figure 127: out of Step Detection Characteristic273
- Out of Step Protection Operataing Principle274
- Out of Step Logic Diagram275
- OST Application Notes275
- Setting the OST Mode275
- Figure 128: out of Step Logic Diagram275
- Figure 129: OST Setting Determination for the Positive Sequence Resistive Component OST R5276
- Figure 130: OST R6Max Determination277
- Figure 131: Example of Timer Reset Due to Movs Operation280
Chapter 11 Autoreclose281
Chapter Overview283
Introduction to Autoreclose284
Autoreclose Implementation285
- Autoreclose Logic Inputs from External Sources286
- Circuit Breaker Healthy Input286
- Inhibit Autoreclose Input286
- Block Autoreclose Input286
- Reset Lockout Input287
- Pole Discrepancy Input287
- External Trip Indication287
- Autoreclose Logic Inputs287
- Trip Initiation Signals287
- Circuit Breaker Status Inputs287
- System Check Signals287
- Autoreclose Logic Outputs287
- Autoreclose Operating Sequence288
- AR Timing Sequence - Transient Fault288
- AR Timing Sequence - Evolving/Permanent Fault288
- Figure 132: Autoreclose Sequence for a Transient Fault288
- AR Timing Sequence - Evolving/Permanent Fault Single-Phase289
- AR Timing Sequence - Transient Fault Dual CB289
- Figure 133: Autoreclose Sequence for an Evolving or Permanent Fault289
- Figure 134: Autoreclose Sequence for an Evolving or Permanent Fault - Single-Phase Operation289
- AR Timing Sequence - Evolving/Permanent Fault Dual CB290
- Figure 135: Dual CB Autoreclose Sequence for a Transient Fault290
- AR Timing Sequence - Persistent Fault291
- Figure 136: Autoreclose Sequence for an Evolving/Permanent Fault on a Dual CB Application291
- Figure 137: Autoreclose Sequence for a Persistent Fault on a Multishot Dual CB Application Set291
Autoreclose System Map293
- Figure 138: Key to Logic Diagrams294
- Autoreclose System Map Diagrams295
- Figure 139: Autoreclose System Map - Part 1295
- Figure 140: Autoreclose System Map - Part297
- Figure 144: Autoreclose System Map - Part 6300
- Figure 141: Autoreclose System Map - Part301
- Figure 142: Autoreclose System Map - Part302
- Figure 143: Autoreclose System Map - Part303
- Autoreclose Internal Signals304
- Figure 148: Autoreclose System Map - Part 10304
- Autoreclose DDB Signals309
Logic Modules321
- Circuit Breaker Status Monitor321
- CB State Monitor322
- Circuit Breaker Open Logic322
- Figure 149: CB State Logic Diagram (Module 1)322
- Circuit Breaker Open Logic Diagram323
- Circuit Breaker in Service Logic323
- Figure 150: Circuit Breaker Open Logic Diagram (Module 3)323
- Circuit Breaker in Service Logic Diagram324
- Autoreclose Enable Logic324
- Autoreclose Enable Logic Diagram324
- Autoreclose Leader/Follower324
- Figure 151: CB in Service Logic Diagram (Module 4)324
- Figure 152: Autoreclose Enable Logic Diagram (Module 5)324
- Leader/Follower CB Selection Logic Diagram325
- Figure 153: Leader/Follower CB Selection Logic Diagram (Module 6)325
- Leader Follower Logic Diagram326
- Figure 154: Leader/Follower Logic Diagram (Module 7 & 8)326
- Autoreclose Modes327
- Single-Phase and Three-Phase Autoreclose327
- Autoreclose Modes Enable Logic Diagram328
- Figure 155: Autoreclose Modes Enable Logic Diagram (Module 9)328
- AR Force Three-Phase Trip Logic329
- Force Three-Phase Trip Logic Diagram329
- Figure 156: Force Three-Phase Trip Logic Diagram (Module 10)329
- Autoreclose Initiation Logic330
- Autoreclose Initiation Logic Diagram331
- Autoreclose Trip Test Logic Diagram331
- Figure 157: Autoreclose Initiation Logic Diagram (Module 11)331
- Figure 158: Autoreclose Trip Test Logic Diagram (Module 12)331
- External Trip Logic Diagram for CB1332
- Figure 159: Autoreclose Initiation by Internal Single and Three Phase Trip or External Trip for CB1332
- External Trip Logic Diagram for CB2333
- Figure 160: Autoreclose Initiation by Internal Single and Three Phase Trip or External Trip for CB2333
- Protection Reoperation and Evolving Fault Logic Diagram334
- Fault Memory Logic Diagram334
- Autoreclose in Progress334
- Figure 161: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)334
- Figure 162: Fault Memory Logic Diagram (Module 15)334
- Autoreclose in Progress Logic Diagram for CB1335
- Figure 163: Autoreclose in Progress Logic Diagram for CB1 (Module 16)335
- Autoreclose in Progress Logic Diagram for CB2336
- Sequence Counter336
- Figure 164: Autoreclose in Progress Logic Diagram for CB2 (Module 17)336
- Autoreclose Sequence Counter Logic Diagram337
- Autoreclose Cycle Selection337
- Figure 165: Autoreclose Sequence Counter Logic Diagram (Module 18)337
- Single Phase Autoreclose Cycle Selection Logic Diagram338
- Figure 166: Single-Phase Autoreclose Cycle Selection Logic Diagram (Module 19)338
- 3-Phase Autoreclose Cycle Selection339
- Dead Time Control339
- Figure 167: Three-Phase Autoreclose Cycle Selection Logic Diagram (Module 21)339
- Dead Time Start Enable Logic Diagram340
- Figure 168: Dead Time Start Enable Logic Diagram (Module 22)340
- Single-Phase Leader Dead Time Logic Diagram341
- Figure 169: Single-Phase Leader Dead Time Logic Diagram (Module 24)341
- 3-Phase Leader Dead Time Logic Diagram342
- Figure 170: Three-Phase Leader CB Dead Time Logic Diagram (Module 25)342
- Follower Enable Logic Diagram343
- Figure 171: Follower Enable Logic Diagram (Module 27)343
- Single-Phase Follower Timing Logic Diagram344
- Figure 172: Single-Phase Follower CB Timing Logic Diagram (Module 28)344
- Three-Phase Follower Timing Logic Diagram345
- Circuit Breaker Autoclose345
- Figure 173: Three-Phase Follower CB Timing Logic Diagram (Module 29)345
- Circuit Breaker Autoclose Logic Diagram346
- Reclaim Time346
- Figure 174: Circuit Breaker Autoclose Logic Diagram (Modules 32 & 33)346
- Prepare Reclaim Initiation Logic Diagram347
- Figure 175: Prepare Reclaim Initiation Logic Diagram (Module 34)347
- Reclaim Time Logic Diagram348
- Figure 176: Reclaim Time Logic Diagram (Module 35)348
- Succesful Autoreclose Signals Logic Diagram349
- Figure 177: Successful Autoreclose Signals Logic Diagram (Module 36)349
- Autoreclose Reset Successful Indication Logic Diagram350
- CB Healthy and System Check Timers350
- Figure 178: Autoreclose Reset Successful Indication Logic Diagram (Modules 37 & 38)350
- CB Healthy and System Check Timers Logic Diagram351
- Autoreclose Shot Counters351
- Figure 179: Circuit Breaker Healthy and System Check Timers Healthy Logic Diagram (Module 39)351
- Autoreclose Shot Counters Logic Diagram353
- Figure 180: Autoreclose Shot Counters Logic Diagram (Modules 41 & 42)353
- Circuit Breaker Control354
- CB Control Logic Diagram354
- Figure 181: CB1 Control Logic (Module 43)354
- Circuit Breaker Trip Time Monitoring355
- Figure 182: CB2 Control Logic (Module 44)355
- CB Trip Time Monitoring Logic Diagram356
- Figure 183: Circuit Breaker Trip Time Monitoring Logic Diagram (Modules 53 & 54)356
- Autoreclose Lockout357
- CB Lockout Logic Diagram358
- Figure 184: CB1 Lockout Logic Diagram (Module 55)358
- Reset Circuit Breaker Lockout359
- Figure 185: CB2 Lockout Logic Diagram (Module 56)359
- Reset CB Lockout Logic Diagram361
- Pole Discrepancy361
- Figure 186: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58)361
- Pole Discrepancy Logic Diagram362
- Circuit Breaker Trip Conversion362
- Figure 187: Pole Discrepancy Logic Diagram (Module 62)362
- CB Trip Conversion Logic Diagram363
- Monitor Checks for CB Closure363
- Figure 188: Circuit Breaker Trip Conversion Logic Diagram (Module 63)363
- Voltage Monitor for CB Closure364
- Figure 189: Voltage Monitor for CB Closure (Module 59)364
- Check Synchronisation Monitor for CB Closure365
- Figure 190: Check Synchronisation Monitor for CB1 Closure (Module 60)365
- Synchronisation Checks for CB Closure366
- Figure 191: Check Synchronisation Monitor for CB2 Closure (Module 61)366
- Three-Phase Autoreclose Leader Check Logic Diagram368
- Figure 192: Three-Phase AR System Check Logic Diagram for CB1 as Leader (Module 45)368
- Figure 193: Three-Phase AR System Check Logic Diagram for CB2 as Leader (Module 46)369
- Three-Phase Autoreclose Follower Check Logic Diagram370
- Figure 194: Three-Phase AR System Check Logic D for CB1 as Follower (Module 47)370
- Figure 195: Three-Phase AR System Check Logic Diagram for CB2 as Follower (Module 48)371
- CB Manual Close System Check Logic Diagram372
- Figure 196: CB Manual Close System Check Logic Diagram (Modules 51 & 52)372
Setting Guidelines373
- De-Ionising Time Guidance373
- Dead Timer Setting Guidelines373
- Example Dead Time Calculation373
- Reclaim Time Setting Guidelines374
- Autoreclose Shot Counters374
Chapter 12 CB Fail Protection377
Chapter Overview379
Circuit Breaker Fail Protection380
Circuit Breaker Fail Implementation381
- Circuit Breaker Fail Timers381
- Zero Crossing Detection381
Circuit Breaker Fail Logic - Part383
- Circuit Breaker Fail Logic - Part384
- Circuit Breaker Fail Logic - Part 3385
- Figure 200: Circuit Breaker Fail Logic - Part 4386
- Circuit Breaker Fail Logic - Part 4386
Application Notes387
- Reset Mechanisms for CB Fail Timers387
- Setting Guidelines (CB Fail Timer)387
- Setting Guidelines (Undercurrent)388
- Figure 201: CB Fail Timing388
Chapter 13 Current Protection Functions389
Chapter Overview391
Phase Fault Overcurrent Protection392
- POC Implementation392
- Directional Element392
- POC Logic394
- Figure 202: Phase Overcurrent Protection Logic Diagram394
Negative Sequence Overcurrent Protection395
- Negative Sequence Overcurrent Protection Implementation395
- Directional Element395
- NPSOC Logic396
- Application Notes396
- Setting Guidelines (Current Threshold)396
- Setting Guidelines (Time Delay)396
- Setting Guidelines (Directional Element)396
- Figure 203: Negative Phase Sequence Overcurrent Protection Logic Diagram396
Earth Fault Protection398
- Earth Fault Protection Implementation398
- IDG Curve398
- Directional Element399
- Residual Voltage Polarisation399
- Figure 204: IDG Characteristic399
- Negative Sequence Polarisation400
- Earth Fault Protection Logic401
- Application Notes401
- Residual Voltage Polarisation Setting Guidelines401
- Setting Guidelines (Directional Element)401
- Figure 205: Earth Fault Protection Logic Diagram401
Sensitive Earth Fault Protection403
- SEF Protection Implementation403
- EPATR B Curve403
- Sensitive Earth Fault Protection Logic404
- Figure 206: EPATR B Characteristic Shown for TMS = 1.0404
- Figure 207: Sensitive Earth Fault Protection Logic Diagram404
- Application Notes405
- Insulated Systems405
- Figure 208: Current Distribution in an Insulated System with C Phase Fault405
- Setting Guidelines (Insulated Systems)406
- Figure 209: Phasor Diagrams for Insulated System with C Phase Fault406
- Figure 210: Positioning of Core Balance Current Transformers407
High Impedance REF408
- High Impedance REF Principle408
- Figure 211: High Impedance REF Principle408
- Figure 212: High Impedance REF Connection409
Thermal Overload Protection410
- Single Time Constant Characteristic410
- Dual Time Constant Characteristic410
- Thermal Overload Protection Implementation411
- Thermal Overload Protection Logic411
- Application Notes411
- Setting Guidelines for Dual Time Constant Characteristic411
- Figure 213: Thermal Overload Protection Logic Diagram411
- Figure 214: Spreadsheet Calculation for Dual Time Constant Thermal Characteristic412
- Figure 215: Dual Time Constant Thermal Characteristic412
- Setting Guidelines for Single Time Constant Characteristic413
Broken Conductor Protection414
- Broken Conductor Protection Implementation414
- Broken Conductor Protection Logic414
- Application Notes414
- Setting Guidelines414
- Figure 216: Broken Conductor Logic414
Chapter 14 Voltage Protection Functions417
Chapter Overview419
Undervoltage Protection420
- Undervoltage Protection Implementation420
- Undervoltage Protection Logic421
- Figure 217: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)421
- Application Notes422
- Undervoltage Setting Guidelines422
Overvoltage Protection423
- Overvoltage Protection Implementation423
- Overvoltage Protection Logic424
- Figure 218: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)424
- Application Notes425
- Overvoltage Setting Guidelines425
Compensated Overvoltage426
Residual Overvoltage Protection427
- Residual Overvoltage Protection Implementation427
- Residual Overvoltage Logic428
- Application Notes428
- Calculation for Solidly Earthed Systems428
- Figure 219: Residual Overvoltage Logic428
- Calculation for Impedance Earthed Systems429
- Figure 220: Residual Voltage for a Solidly Earthed System429
- Setting Guidelines430
- Figure 221: Residual Voltage for an Impedance Earthed System430
Chapter 15 Frequency Protection Functions431
Chapter Overview433
Frequency Protection434
- Underfrequency Protection434
- Underfrequency Protection Implementation434
- Underfrequency Protection Logic435
- Application Notes435
- Overfrequency Protection435
- Overfrequency Protection Implementation435
- Figure 222: Underfrequency Logic (Single Stage)435
- Overfrequency Protection Logic436
- Application Notes436
- Figure 223: Overfrequency Logic (Single Stage)436
Independent R.O.C.O.F Protection437
- Indepenent R.O.C.O.F Protection Implementation437
- Independent R.O.C.O.F Protection Logic437
- Figure 224: Rate of Change of Frequency Logic (Single Stage)437
Chapter 16 Monitoring and Control439
Chapter Overview441
Event Records442
- Event Types442
- Opto-Input Events443
- Contact Events443
- Alarm Events443
- Fault Record Events444
- Maintenance Events444
- Protection Events444
- Figure 225: Fault Recorder Stop Conditions444
- Security Events445
- Platform Events445
Disturbance Recorder446
Measurements447
- Measured Quantities447
- Measurement Setup447
- Fault Locator447
- Opto-Input Time Stamping447
CB Condition Monitoring448
- Broken Current Accumulator449
- Figure 226: Broken Current Accumulator Logic Diagram449
- CB Trip Counter450
- Figure 227: CB Trip Counter Logic Diagram450
- CB Operating Time Accumulator451
- Figure 228: Operating Time Accumulator451
- Excessive Fault Frequency Counter452
- Figure 229: Excessive Fault Frequency Logic Diagram452
- Reset Lockout Alarm453
- Figure 230: Reset Lockout Alarm Logic Diagram453
- CB Condition Monitoring Logic454
- Figure 231: CB1 Condition Monitoring Logic Diagram454
- Reset Circuit Breaker Lockout455
- Figure 232: CB2 Condition Monitoring Logic Diagram455
- Reset CB Lockout Logic Diagram457
- Application Notes457
- Setting the Thresholds for the Total Broken Current457
- Figure 233: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58)457
- Setting the Thresholds for the Number of Operations458
- Setting the Thresholds for the Operating Time458
- Setting the Thresholds for Excesssive Fault Frequency458
CB State Monitoring459
- CB State Monitor460
- Figure 234: CB State Logic Diagram (Module 1)460
Circuit Breaker Control461
- CB Control Using the IED Menu461
- CB Control Using the Hotkeys462
- CB Control Using the Function Keys462
- Figure 235: Hotkey Menu Navigation462
- CB Control Using the Opto-Inputs463
- Remote CB Control463
- Figure 236: Default Function Key PSL463
- CB Healthy Check464
- Synchronisation Check464
- CB Control AR Implications464
- Figure 237: Remote Control of Circuit Breaker464
- CB Control Logic Diagram465
- Figure 238: CB1 Control Logic (Module 43)465
- Figure 239: CB2 Control Logic (Module 44)466
Pole Dead Function467
- Pole Dead Logic467
- Figure 240: Pole Dead Logic467
System Checks468
- System Checks Implementation468
- VT Connections468
- Voltage Monitoring469
- Check Synchronisation469
- Check Syncronisation Vector Diagram469
- Figure 241: Check Synchronisation Vector Diagram470
- Voltage Monitor for CB Closure471
- Figure 242: Voltage Monitor for CB Closure (Module 59)471
- Check Synchronisation Monitor for CB Closure472
- Figure 243: Check Synchronisation Monitor for CB1 Closure (Module 60)472
- Figure 244: Check Synchronisation Monitor for CB2 Closure (Module 61)473
- System Check PSL474
- Application Notes474
- Predictive Closure of Circuit Breakers474
- Voltage and Phase Angle Correction474
- Figure 245: System Check PSL474
Chapter 17 Supervision477
Chapter Overview479
Voltage Transformer Supervision480
- Loss of One or Two Phase Voltages480
- Loss of All Three Phase Voltages480
- Absence of All Three Phase Voltages on Line Energisation480
- VTS Implementation481
- VTS Logic482
- Figure 246: VTS Logic482
Current Transformer Supervision484
- CTS Implementation484
- Standard CTS Logic485
- CTS Blocking485
- Application Notes485
- Setting Guidelines485
- Figure 247: Standard CTS485
Trip Circuit Supervision486
- Trip Circuit Supervision Scheme486
- Resistor Values486
- Figure 248: TCS Scheme 1486
- Psl for Tcs Scheme 1487
- Trip Circuit Supervision Scheme487
- Figure 249: PSL for TCS Scheme 1487
- Resistor Values488
- Psl for Tcs Scheme 2488
- Trip Circuit Supervision Scheme488
- Figure 251: PSL for TCS Scheme 2488
- Figure 252: TCS Scheme 3488
- Resistor Values489
- Psl for Tcs Scheme 3489
- Figure 253: PSL for TCS Scheme 3489
Chapter 18 Digital I/O and PSL Configuration491
Chapter Overview493
Configuring Digital Inputs and Outputs494
Scheme Logic495
- Figure 254: Scheme Logic Interfaces495
- PSL Editor496
- PSL Schemes496
- PSL Scheme Version Control496
Configuring the Opto-Inputs497
Assigning the Output Relays498
Fixed Function Leds499
- Trip LED Logic499
- Figure 255: Trip LED Logic499
Configuring Programmable Leds500
Function Keys502
Control Inputs503
Chapter 19 Fibre Teleprotection505
Chapter Overview507
Protection Signalling Introduction508
- Unit Protection Schemes508
- Teleprotection Commands508
- Transmission Media and Interference509
Fibre Teleprotection Implementation510
- Setting up the IM64 Scheme510
- Fibre Teleprotection Scheme Terminal Addressing511
- Figure 256: Fibre Teleprotection Connections for a Three-Terminal Scheme511
- Setting up IM64512
- Two-Terminal IM64 Operation512
- Dual Redundant Two-Terminal IM64 Operation512
- Three-Terminal IM64 Operation512
- Physical Connection513
- Figure 257: Interfacing to PCM Multiplexers515
IM64 Logic517
- Figure 258: IM64 Channel Fail and Scheme Fail Logic517
- Figure 259: IM64 General Alarm Signals Logic517
- Figure 260: IM64 Communications Mode and IEEE C37.94 Alarm Signals518
Application Notes519
- Alarm Management519
- Alarm Logic519
- Two-Ended Scheme Extended Supervision520
- Three-Ended Scheme Extended Supervision520
- Figure 261: IM64 Two-Terminal Scheme Extended Supervision520
- Figure 262: IM64 Three-Terminal Scheme Extended Supervision520
Chapter 20 Electrical Teleprotection523
Chapter Overview525
Introduction526
Teleprotection Scheme Principles527
- Direct Tripping527
- Permissive Tripping527
Implementation528
Configuration529
- Figure 263: Example Assignment of Intermicom Signals Within the PSL530
Connecting to Electrical Intermicom531
- Short Distance531
- Long Distance531
- Figure 264: Direct Connection531
- Figure 265: Indirect Connection Using Modems531
Application Notes532
Chapter 21 Communications535
Chapter Overview537
Communication Interfaces538
Serial Communication539
- EIA(RS)232 Bus539
- EIA(RS)485 Bus539
- EIA(RS)485 Biasing Requirements540
- K-Bus540
- Figure 266: RS485 Biasing Circuit540
- Figure 267: Remote Communication Using K-Bus541
Standard Ethernet Communication542
- Hot-Standby Ethernet Failover542
Redundant Ethernet Communication543
- Supported Protocols543
- Parallel Redundancy Protocol544
- Figure 268: IED Attached to Separate Lans544
- High-Availability Seamless Redundancy (HSR)545
- HSR Multicast Topology545
- HSR Unicast Topology545
- Figure 269: HSR Multicast Topology545
- HSR Application in the Substation546
- Figure 270: HSR Unicast Topology546
- Rapid Spanning Tree Protocol547
- Figure 271: HSR Application in the Substation547
- Figure 272: IED Attached to Redundant Ethernet Star or Ring Circuit547
- Self Healing Protocol548
- Figure 273: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities548
- Figure 274: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches548
- Dual Homing Protocol549
- Figure 275: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches549
- Figure 276: Dual Homing Mechanism550
- Configuring IP Addresses551
- Figure 277: Application of Dual Homing Star at Substation Level551
- Configuring the IED IP Address552
- Configuring the REB IP Address552
- Figure 278: IED and REB IP Address Configuration552
- PRP/HSR Configurator554
- Connecting the IED to a PC555
- Installing the Configurator555
- Starting the Configurator555
- Figure 279: Connection Using (A) an Ethernet Switch and (B) a Media Converter555
- PRP/HSR Device Identification556
- Selecting the Device Mode556
- PRP/HSR IP Address Configuration556
- SNTP IP Address Configuration556
- Check for Connected Equipment556
- PRP Configuration556
- HSR Configuration557
- Filtering Database557
- End of Session558
- RSTP Configurator558
- Connecting the IED to a PC558
- Installing the Configurator559
- Starting the Configurator559
- RSTP Device Identification559
- Figure 280: Connection Using (A) an Ethernet Switch and (B) a Media Converter559
- RSTP IP Address Configuration560
- SNTP IP Address Configuration560
- Check for Connected Equipment560
- RSTP Configuration560
- End of Session561
- Switch Manager561
- Installation562
- Setup563
- Network Setup563
- Bandwidth Used563
- Reset Counters563
- Check for Connected Equipment563
- Mirroring Function564
- Ports On/Off564
- Vlan564
- End of Session564
Simple Network Management Protocol (SNMP)565
- SNMP Management Information Bases565
- Main Processor MIBS Structure565
- Redundant Ethernet Board MIB Structure566
- Accessing the MIB570
- Main Processor SNMP Configuration570
Data Protocols572
- Courier572
- Physical Connection and Link Layer572
- Courier Database573
- Settings Categories573
- Setting Changes573
- Event Extraction573
- Disturbance Record Extraction575
- Programmable Scheme Logic Settings575
- Time Synchronisation575
- Courier Configuration576
- Physical Connection and Link Layer577
- Iec 60870-5-103577
- Initialisation578
- Time Synchronisation578
- Spontaneous Events578
- General Interrogation (GI)578
- Cyclic Measurements578
- Commands578
- Test Mode579
- Disturbance Records579
- Command/Monitor Blocking579
- IEC 60870-5-103 Configuration579
- Dnp580
- Physical Connection and Link Layer580
- Object 1 Binary Inputs581
- Object 10 Binary Outputs581
- Object 20 Binary Counters582
- Object 30 Analogue Input582
- Figure 281: Control Input Behaviour582
- Object 40 Analogue Output583
- Object 50 Time Synchronisation583
- DNP3 Device Profile583
- DNP3 Configuration591
- Iec 61850592
- Benefits of IEC 61850593
- IEC 61850 Interoperability593
- The IEC 61850 Data Model593
- IEC 61850 in Micom Ieds594
- Figure 282: Data Model Layers in IEC61850594
- IEC 61850 Data Model Implementation595
- IEC 61850 Communication Services Implementation595
- IEC 61850 Peer-To-Peer (GOOSE) Communications595
- Mapping GOOSE Messages to Virtual Inputs595
- Ethernet Functionality596
- IEC 61850 Configuration596
- Iec 61850 Edition 2597
- Figure 283: Edition 2 System - Backward Compatibility598
- Figure 284: Edition 1 System - Forward Compatibility Issues598
- Figure 285: Example of Standby IED599
- Figure 286: Standby IED Activation Process600
Read Only Mode601
- Courier Protocol Blocking601
- IEC 61850 Protocol Blocking602
- Read-Only Settings602
- Read-Only DDB Signals602
Time Synchronisation603
- Demodulated IRIG-B603
- IRIG-B Implementation603
- Figure 287: GPS Satellite Timing Signal603
- Sntp604
- Loss of SNTP Server Signal Alarm604
- IEEE 1588 Precision Time Protocol604
- Accuracy and Delay Calculation604
- PTP Domains605
- Time Synchronsiation Using the Communication Protocols605
- Figure 288: Timing Error Using Ring or Line Topology605
Chapter 22 Cyber-Security607
Overview609
The Need for Cyber-Security610
Standards611
- NERC Compliance611
- Cip 002612
- Cip 007613
- Ieee 1686-2007613
Cyber-Security Implementation615
- NERC-Compliant Display615
- Four-Level Access616
- Figure 289: Default Display Navigation616
- Blank Passwords617
- Password Rules618
- Access Level Ddbs618
- Enhanced Password Security618
- Password Strengthening618
- Password Validation619
- Password Blocking619
- Password Recovery620
- Password Encryption621
- Disabling Physical Ports621
- Disabling Logical Ports621
- Security Events Management622
- Logging out624
Chapter 23 Installation625
Chapter Overview627
Handling the Goods628
- Receipt of the Goods628
- Unpacking the Goods628
- Storing the Goods628
- Dismantling the Goods628
Mounting the Device629
- Flush Panel Mounting629
- Figure 290: Location of Battery Isolation Strip629
- Rack Mounting630
- Figure 291: Rack Mounting of Products630
Cables and Connectors632
- Terminal Blocks632
- Figure 292: Terminal Block Types632
- Power Supply Connections633
- Earth Connnection633
- Watchdog Connections633
- EIA(RS)485 and K-Bus Connections633
- IRIG-B Connection634
- Opto-Input Connections634
- Output Relay Connections634
- Ethernet Metallic Connections634
- Ethernet Fibre Connections634
- RS232 Connection635
- Download/Monitor Port635
- GPS Fibre Connection635
- Fibre Communication Connections635
Case Dimensions636
- Case Dimensions 40TE636
- Figure 293: 40TE Case Dimensions636
Chapter 24 Commissioning Instructions637
Chapter Overview639
General Guidelines640
Commissioning Test Menu641
- Opto I/P Status Cell (Opto-Input Status)641
- Relay O/P Status Cell (Relay Output Status)641
- Test Port Status Cell641
- Monitor Bit 1 to 8 Cells641
- Test Mode Cell642
- Test Pattern Cell642
- Contact Test Cell642
- Test Leds Cell642
- Test Autoreclose Cell642
- Static Test Mode643
- Loopback Mode643
- IM64 Test Pattern644
- IM64 Test Mode644
- Red and Green LED Status Cells644
- Using a Monitor Port Test Box644
Commissioning Equipment645
- Recommended Commissioning Equipment645
- Essential Commissioning Equipment645
- Advisory Test Equipment646
Product Checks647
- Product Checks with the IED De-Energised647
- Visual Inspection648
- Current Transformer Shorting Contacts648
- Insulation648
- External Wiring648
- Watchdog Contacts649
- Power Supply649
- Product Checks with the IED Energised649
- Test LCD650
- Date and Time650
- Test Leds651
- Test Alarm and Out-Of-Service Leds651
- Test Trip LED651
- Test User-Programmable Leds651
- Test Opto-Inputs651
- Test Output Relays651
- Test Serial Communication Port RP1652
- Figure 294: RP1 Physical Connection652
- Test Serial Communication Port RP2653
- Test Ethernet Communication653
- Figure 295: Remote Communication Using K-Bus653
- Secondary Injection Tests654
- Test Current Inputs654
- Test Voltage Inputs654
Electrical Intermicom Communication Loopback656
- Setting up the Loopback656
- Loopback Test656
- Figure 296: Intermicom Loopback Testing656
- Intermicom Command Bits657
- Intermicom Channel Diagnostics657
- Simulating a Channel Failure657
Intermicom 64 Communication658
- Checking the Interface658
- Setting up the Loopback659
- Loopback Test659
Setting Checks660
- Apply Application-Specific Settings660
- Transferring Settings from a Settings File660
- Entering Settings Using the HMI660
IEC 61850 Edition 2 Testing662
- Using IEC 61850 Edition 2 Test Modes662
- IED Test Mode Behaviour662
- Sampled Value Test Mode Behaviour662
- Simulated Input Behaviour663
- Testing Examples663
- Figure 297: Simulated Input Behaviour663
- Test Procedure for Real Values664
- Test Procedure for Simulated Values - no Plant664
- Figure 298: Test Example 1664
- Test Procedure for Simulated Values - with Plant665
- Figure 299: Test Example 2665
- Contact Test666
- Figure 300: Test Example 3666
Distance Protection667
- Single-Ended Testing667
- Preliminaries667
- Zone 1 Reach Check667
- Zone 2 Reach Check668
- Zone 3 Reach Check668
- Zone 4 Reach Check668
- Zone P Reach Check668
- Resistive Reach669
- Load Blinder669
- Operation and Contact Assignment669
- Phase a669
- Phase B669
- Phase C669
- Time Delay Settings670
- Scheme Testing670
- Scheme Trip Test for Zone 1 Extension671
- Scheme Trip Tests for Permissive Schemes671
- Scheme Trip Tests for Blocking Scheme671
- Signal Send Test for Permissive Schemes672
- Signal Send Test for Blocking Scheme672
- Scheme Timer Settings672
Delta Directional Comparison673
- Single-Ended Testing673
- Preliminaries673
- Single-Ended Injection Test673
- Forward Fault Preparation673
- Operation and Contact Assignment674
- Phase a674
- Phase B674
- Phase C674
- Delta Protection Scheme Testing675
- Signal Send Test for Permissive Schemes675
- Signal Send Test for Blocking Schemes675
DEF Aided Schemes676
- Earth Current Pilot Scheme676
- Preliminaries676
- Perform the Test676
- Forward Fault Trip Test677
- Scheme Testing677
- Signal Send Test for Permissive Schemes677
- Signal Send Test for Blocking Schemes677
Out of Step Protection678
- OST Setting678
- Figure 301: State Impedances678
- Predictive OST Setting679
- Predictive and OST Setting679
- OST Timer Test679
Protection Timing Checks680
- Overcurrent Check680
- Connecting the Test Circuit680
- Performing the Test680
- Check the Operating Time680
System Check and Check Synchronism682
- Check Synchronism Pass682
- Check Synchronism Fail682
Check Trip and Autoreclose Cycle683
End-To-End Communication Tests684
- Remove Local Loopbacks684
- Restoring Direct Fibre Connections684
- Restoring C37.94 Fibre Connections685
- Communications Using P59X Interface Units685
- Remove Remote Loopbacks685
- Verify Communication between Ieds685
End-To-End Scheme Tests687
- Aided Scheme687
- Preparation at Remote End687
- Performing the Test687
- Channel Check in the Opposite Direction687
Onload Checks689
- Confirm Current Connections689
- Confirm Voltage Connections689
- On-Load Directional Test690
Final Checks691
Commmissioning the P59X692
- Visual Inspection692
- Insulation692
- External Wiring692
- P59X Auxiliary Supply692
- P59X Leds693
- Received Optical Signal Level693
- Optical Transmitter Level693
- Loopback Test694
Chapter 25 Maintenance and Troubleshooting695
Chapter Overview697
Maintenance698
- Maintenance Checks698
- Alarms698
- Opto-Isolators698
- Output Relays698
- Measurement Accuracy698
- Replacing the Device699
- Repairing the Device700
- Removing the Front Panel700
- Figure 302: Possible Terminal Block Types700
- Replacing Pcbs701
- Replacing the Main Processor Board701
- Replacement of Communications Boards702
- Figure 303: Front Panel Assembly702
- Replacement of the Input Module703
- Replacement of the Power Supply Board703
- Replacement of the I/O Boards704
- Recalibration704
- Changing the Battery704
- Post Modification Tests705
- Battery Disposal705
- Cleaning705
Troubleshooting706
- Self-Diagnostic Software706
- Power-Up Errors706
- Error Message or Code on Power-Up706
- Out of Service LED on at Power-Up707
- Error Code During Operation708
- Backup Battery708
- Mal-Operation During Testing708
- Failure of Output Contacts708
- Failure of Opto-Inputs708
- Incorrect Analogue Signals709
- Coprocessor Board Failures709
- Signalling Failure Alarm (on Its Own)709
- C Diff Failure Alarm (on Its Own)709
- Signalling Failure and C Diff Failure Alarms Together709
- Incompatible IED709
- Comms Changed709
- IEEE C37.94 Fail710
- PSL Editor Troubleshooting710
- Diagram Reconstruction710
- PSL Version Check710
- Repair and Modification Procedure710
Chapter 26 Technical Specifications713
Chapter Overview715
Interfaces716
- Front Serial Port716
- Download/Monitor Port716
- Rear Serial Port716
- Fibre Rear Serial Port716
- Optional Rear Serial Port (SK5)717
- IRIG-B (Demodulated)717
- IRIG-B (Modulated)717
- Rear Serial Port 2717
- Rear Ethernet Port Copper718
- Rear Ethernet Port Fibre718
- 100 Base Fx Receiver Characteristics718
- 100 Base Fx Transmitter Characteristics719
- PPS Port719
- Fibre Teleprotection Interface719
Protection Functions720
- Distance Protection720
- Power Swing Blocking720
- Out of Step Protection721
- Fibre Teleprotection Transfer Times721
- Autoreclose and Check Synychronism721
- Phase Overcurrent Protection721
- Transient Overreach and Overshoot722
- Phase Overcurrent Directional Parameters722
- Earth Fault Protection722
- Earth Fault Directional Parameters722
- Sensitive Earth Fault Protection723
- Sensitive Earth Fault Protection Directional Element723
- High Impedance Restricted Earth Fault Protection723
- Negative Sequence Overcurrent Protection723
- NPSOC Directional Parameters724
- Circuit Breaker Fail and Undercurrent Protection724
- Broken Conductor Protection724
- Thermal Overload Protection724
Monitoring, Control and Supervision725
- Voltage Transformer Supervision725
- Standard Current Transformer Supervision725
- Differential Current Transformer Supervision725
- CB State and Condition Monitoring725
- PSL Timers726
Measurements and Recording727
- General727
- Disturbance Records727
- Event, Fault and Maintenance Records727
- Fault Locator727
Ratings728
- AC Measuring Inputs728
- Current Transformer Inputs728
- Voltage Transformer Inputs728
- Auxiliary Supply Voltage728
- Nominal Burden729
- Power Supply Interruption729
- Battery Backup730
Input / Output Connections731
- Isolated Digital Inputs731
- Nominal Pickup and Reset Thresholds731
- Standard Output Contacts731
- High Break Output Contacts732
- Watchdog Contacts732
Mechanical Specifications733
- Physical Parameters733
- Enclosure Protection733
- Mechanical Robustness733
- Transit Packaging Performance733
Type Tests734
- Insulation734
- Creepage Distances and Clearances734
- High Voltage (Dielectric) Withstand734
- Impulse Voltage Withstand Test734
Environmental Conditions735
- Ambient Temperature Range735
- Temperature Endurance Test735
- Ambient Humidity Range735
- Corrosive Environments735
Electromagnetic Compatibility736
- Mhz Burst High Frequency Disturbance Test736
- Damped Oscillatory Test736
- Immunity to Electrostatic Discharge736
- Electrical Fast Transient or Burst Requirements736
- Surge Withstand Capability736
- Surge Immunity Test737
- Immunity to Radiated Electromagnetic Energy737
- Radiated Immunity from Digital Communications737
- Radiated Immunity from Digital Radio Telephones737
- Immunity to Conducted Disturbances Induced by Radio Frequency Fields737
- Magnetic Field Immunity738
- Conducted Emissions738
- Radiated Emissions738
- Power Frequency738
Regulatory Compliance739
- EMC Compliance: 2014/30/EU739
- LVD Compliance: 2014/35/EU739
- R&TTE Compliance: 2014/53/EU739
- UL/CUL Compliance739
- ATEX Compliance: 2014/34/EU739
Appendix A Ordering Options741
Appendix B Settings and Signals745
Appendix C Wiring Diagrams745

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