Test Descriptions
Test
13.
DIRECT COMMAND
--
Tests
the
data paths
that
carry a direct command to the L-Bus.
The testing sequence follows:
1)
Writes an INIT to reset
the
board and clear the FIFO.
2)
Sets up
the
Diagnostic Control Register (Register
!A)
with
timeouts disabled, ROM Test
2,
LOOPEN off, and Free Running The State Machine switches between L-Bus States 0 and
4 because Board Enable
is
off.
3)
Writes an illegal port pointer to the Port Pointer Register. This prevents the L-Bus
handshake
by
holding
off
the
BUSGO signal on the TIC.
4)
Issues
the
Direct command. This takes the L-Bus State Machine
out
of
State
O.
5)
The L-Bus State Machine
then
halts in State
5,
waiting for a BUSEND. The
BUS
END will
not occur and a timeout will result,
but
the
timeouts
are
disabled
so
that
the
error
bits
are
not set. Checks
that
the POLL bit indicates
that
a direct command
is
being executed
(POLL not active).
6)
Writes to the Diagnostic Control Register
(!A)
and sets LOOPEN. This allows the L-Bus
State Machine to continue and
ROM Test 2 will be executed, writing the Direct command
back into the
SIB
memory where
it
may be checked for accuracy.
Test
14.
FIFO
--
Tests
the
operation of the FIFO.
It
checks the following:
1)
that
an
interrupt
is
not present
after
channel INIT;
2)
that
an
interrupt
is
present
after
State 0 of the L-Bus State Machine;
3)
that
the
interrupt
goes
away
after
Register 9
is
read. A read of Register 9 will clear the
current
interrupts.
4)
that
the
correct port
data
is
passed through the FIFO; and
5)
that
an indication
is
received when the FIFO
is
fulL
The
FIFO stores the number
of
each
interrupting
port and
is
three
deep.
Test IS.
STATP.
COUNTER
--
Checks
that
the
DMA state counter increments each time until it
reaches the
halt
command,
at
which point
it
resets to zero.
Test
16.
DMA ADDRESS COUNTER
--
Tests the DMA address counter by checking each bit
carry
as
it
counts.
Test
17.
COMP/CTR LOOPBACK
--
Tests the DMA logic's COMP register and address counter.
It
loads a
pattern
into memory, runs the DMA test
that
loads
the
DMA registers from memory,
and
then
runs the test which dumps the registers back into memory.
Test
18.
READ
1MB
--- Verifies proper operation during an
1MB
read.
It
uses the diagnostic DMA
routine (DMA test
4)
that
reads a single word from the
1MB
and puts
it
in
SIB
RAM. The
data
is
then
checked.
Test
19.
WRITE
1MB
--
Verifies proper operation during an
1MB
write.
It
uses
the
diagnostic DMA
routine (DMA test
5)
that
writes a single word from
SIB
RAM into main memory.
SEP 84
3-3
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