Intel i960 Series

A INDEX
Index-i
B
Bandwidths 3-6
baud rates
on the serial port
3-9
C
Centronics interface 4-5
chip selects 4-3
CIO 3-11
specific usage 3-11
C-language compilers 2-1
Clock Generation 4-1
Clock Signals 4-1
Column Address Strobes 4-7
Console Serial Port 3-9
console serial port 3-9
Counter I/O Unit (CIO) 3-11
CPU module
installation
3-3
memory map 3-4
VPP switch 3-4
D
data signals 4-4
DB960 2-1
deadlock 3-27
debug monitor (MON960) 2-1
Dedicated Interrupt Signals 3-8
DMA chaining mode 3-33
DMA Channel non-chaining mode 3-32
DMA Channel programming 3-32
DMA controller 3-5
DMA Transfer Size Register 3-32
doorbell registers 3-31
DOS support 2-1
DRAM
burst buses
4-6
early write cycles 4-6
features 4-1, 4-6
interleaved 3-5
page mode 4-6
performance 3-6
upgrading SIMMs 3-6
wait state performance 4-7
DRAM controller 4-8
DRAM design
performance
4-7
SIMMs 3-6
DRAM Memory 3-5
DRAM Speed 3-6
Driver/Receiver, RS-232 4-6
E
EEPROM Memory 3-14
EPROM
support for
4-1
Expansion Bus (X-Bus) 3-2
Expansion ROM 3-7
F
Features
functional blocks
4-1
I/O design 4-2
modem support 4-6
FLASH
programming voltage
2-2
support for 4-1
Flash memory 3-7
Flex Logic 4-8
G
GDB960 2-1
GNU/960 2-1