Intel i960 Series User Manual

INDEX A
Index-ii
H
HDIL 2-1
Host communications 2-2
Host Debugger Interface Library (HDIL) 2-1
I
I/O data buffer control 4-3
I/O subsystem
features
4-1
interleaved DRAM 3-5
Interleaving 4-7
Interrupt Control and Status Register 3-28
interrupts 3-8
L
LED (RED, GREEN) 3-2
LEDs
power (green)
4-2
LEDs, user 3-2
Local Configuration Registers 3-16
Local DMA Registers 3-16
Local Init Status bit 3-28
M
Mailbox registers 3-31
MAX232 4-6
memory system performance 4-7
MON960 2-1
MONDB.EXE utility 2-1
O
operating systems
DOS and UNIX
2-1
P
parallel port
bit assignments
3-10
control register bit assignments 3-11
data lines 4-5
handshaking lines 4-5
interrupts 4-5
timing relationships 4-5
Parallel Port (Centronics-compatible) 3-2
Parallel port control register 3-10, 4-5
Parallel port data register 3-10, 4-5
parallel port interrupt 3-10
parallel port interrupt enable bit 3-10
Parallel port status register 3-10, 4-5
PCI Configuration Registers 3-16
PCI interrupts 3-28
peripheral I/O 4-4
PINTEN 3-10
PLL, Internal 4-1
Power (+5 VDC) 3-2
Power (+5 VDC, +12 VDC) 3-2
Presence Detect Signals 3-7
R
reset push-button 4-2
Reset Strobe 4-2
RS-232 port 3-9
S
serial port 4-6
interface 4-6
TXD, RXD, CTS, RTS 4-6
Serial Port (RS-232) 3-2
serial port configuration 2-2
Shared Run Time Registers 3-16
SIMM 3-6
SIMM sockets 3-5

Intel i960 Series Specifications

General

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English

Summary

CHAPTER 1 INTRODUCTION

1.3 TECHNICAL SUPPORT, SCHEMATICS AND PLD EQUATIONS

Provides contact info for support and resource download.

CHAPTER 2 GETTING STARTED

2.1 PRE-INSTALLATION CONSIDERATIONS

Details components and prerequisites for developing programs on the Cyclone EP.

2.2 SOFTWARE INSTALLATION

Guides users through installing necessary development tools and software.

2.3 HARDWARE INSTALLATION

Provides step-by-step instructions for setting up the Cyclone EP hardware.

2.4 CREATING AND DOWNLOADING THE EXAMPLE PROGRAM

Explains how to compile, link, and load an example program.

CHAPTER 3 HARDWARE REFERENCE

3.1 CONNECTORS, SWITCHES AND LEDS

3.2 CPU MODULES

3.3 CPU MEMORY MAP

Illustrates the organization of memory addresses for the i960 processors.

3.4 INTERLEAVED DRAM

3.5 FLASH MEMORY

3.6 INTERRUPTS

Details the interrupt sources and their mapping on the Cyclone EP.

3.7 CONSOLE SERIAL PORT

3.8 PARALLEL PORT

3.11 SQUALL II MODULE INTERFACE

3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)

Explains the PCI bus interface and the PLX 9060 chip.

CHAPTER 4 THEORY OF OPERATION

4.2 CLOCK GENERATION

4.3 POWER MONITOR AND RESET

4.4 I/O INTERFACE

Details the design and implementation of the I/O subsystem and peripherals.

4.5 DRAM SUBSYSTEM

Explains the DRAM controller, memory access, and performance characteristics.

CHAPTER 5 SQUALL II MODULE INTERFACE

5.4 SQUALL II MODULE SIGNAL DEFINITIONS

5.5 SQUALL MODULE SIGNAL DESCRIPTIONS

5.6 SQUALL II MODULE TIMING