Intel i960 Series - Page 12

INDEX A
Index-ii
H
HDIL 2-1
Host communications 2-2
Host Debugger Interface Library (HDIL) 2-1
I
I/O data buffer control 4-3
I/O subsystem
features
4-1
interleaved DRAM 3-5
Interleaving 4-7
Interrupt Control and Status Register 3-28
interrupts 3-8
L
LED (RED, GREEN) 3-2
LEDs
power (green)
4-2
LEDs, user 3-2
Local Configuration Registers 3-16
Local DMA Registers 3-16
Local Init Status bit 3-28
M
Mailbox registers 3-31
MAX232 4-6
memory system performance 4-7
MON960 2-1
MONDB.EXE utility 2-1
O
operating systems
DOS and UNIX
2-1
P
parallel port
bit assignments
3-10
control register bit assignments 3-11
data lines 4-5
handshaking lines 4-5
interrupts 4-5
timing relationships 4-5
Parallel Port (Centronics-compatible) 3-2
Parallel port control register 3-10, 4-5
Parallel port data register 3-10, 4-5
parallel port interrupt 3-10
parallel port interrupt enable bit 3-10
Parallel port status register 3-10, 4-5
PCI Configuration Registers 3-16
PCI interrupts 3-28
peripheral I/O 4-4
PINTEN 3-10
PLL, Internal 4-1
Power (+5 VDC) 3-2
Power (+5 VDC, +12 VDC) 3-2
Presence Detect Signals 3-7
R
reset push-button 4-2
Reset Strobe 4-2
RS-232 port 3-9
S
serial port 4-6
interface 4-6
TXD, RXD, CTS, RTS 4-6
Serial Port (RS-232) 3-2
serial port configuration 2-2
Shared Run Time Registers 3-16
SIMM 3-6
SIMM sockets 3-5