Intel i960 Series

SQUALL II MODULE INTERFACE A
5-14
Figure 5-7. Squall II Master Read and Write Timing Diagram
1 2 3 4 5 6 7 8 9 10
B610.TD
PMCLK
SQBR
SQBG
S_ADS
S_BLAST
S_EXTEND
S_ADDR
S_DATA
S_READY
t2
t1
t9
t2
t9
t9
S_W/R
t2
t1
t11
t10t2
t2
t2
t11
t2
t2
t2
t2
t11
t2
t2
t9
t9
t11
t5
t5
t7
t8
t5
t5
t3
t4