Intel i960 Series User Manual

A SQUALL II MODULE INTERFACE
5-15
Figure 5-8. Squall II Master Burst Read and Write Timing Diagram
Figure 5-9, Squall II Master Read Using S_EXTEND, shows a three clock cycle access. Refresh cycles
may cause READY
to be delayed by up to 10 additional clock cycles.
Read cycle extends by asserting EXTEND
. Valid data is placed on the bus by the DRAM when READY
is asserted. Valid data is held on the bus for every rising clock edge in which EXTEND is asserted.
Cycle ends with BLAST
and READY asserted and EXTEND negated.
D612A.TD
PMCLK
SQBR
SQBG
S_ADS
S_BLAST
S_EXTEND
S_ADDR
S_DATA
S_READY
S_W/R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
t1
t2
t10
t11
t11
t11
t11
t3
t2
t2
t3
t3
t3
t4 t4
t5
t5
t5
t7
t8
t10
t10
t9
t9
t9
t9
t9
t2
t1

Intel i960 Series Specifications

General

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English