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Intel i960 Series User Manual
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SQUALL II MODULE INTERFAC
E
A
5-1
6
Figure 5-9.
Squall II Master Read Using
S_EXTEN
D
D611A.TD
PMCLK
SQBR
SQBG
S_ADS
S_BLAST
S_EXTEND
S_ADDR
S_DATA
S_READY
S_W
/
R
1
2
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S_BEx
t2
t11
t11
t11
t11
t1
t10
t2
t2
t2
t5
t5
t5
t5
t3
t4
t7
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95
Table of Contents
Default Chapter
3
Table of Contents
3
Chapter 1 Introduction
18
Advantages and Features
18
About this Manual
18
Notation Conventions
19
Technical Support, Schematics and Pld Equations
19
Additional Information
20
Chapter 2 Getting Started
21
Pre-Installation Considerations
23
Software Development Tools
23
MON960 Debug Monitor
23
Host Communications
24
Terminal Emulation Method
24
Host Debugger Interface Library (HDIL) Method
24
Source Level Debugger
24
Power Requirements
24
Software Installation
25
Installing Software Development Tools
25
Hardware Installation
25
Verify Cyclone EP Is Functional
25
Creating and Downloading the Example Program
26
MONDB.EXE-To-Cyclone EP Communication Support
26
Terminal Emulation-To-Cyclone EP Communication Support
28
Chapter 3 Hardware Reference
29
Connectors, Switches and Leds
31
Table 3-1 External Connectors and Leds
32
Cpu Modules
33
CPU Module Installation
33
CPU Module Clock Frequencies
33
Table 3-2 CPU Module Frequency Switch Settings
33
I960 Jx/Hx CPU Counter/Timers
34
CPU Module VPP Switch
34
Cpu Memory Map
34
Table 3-3 I960 Jx/Hx CPU Clock Rates
34
Interleaved Dram
35
DRAM Performance
35
Upgrading SIMM DRAM
36
Table 3-4 DRAM Access Times
36
Flash Memory
37
Swaprom Switch
37
Table 3-5 DRAM SIMM Configurations
37
Table 3-6 Flash ROM Addresses
37
Interrupts
38
Table 3-7 Interrupt Sources
38
Table 3-8 80960Sx and Kx Interrupt Sources
38
Console Serial Port
39
Table 3-9 80960Sx and Kx Interrupt Switch Settings
39
Table 3-10 UART Register Addresses
39
Parallel Port
40
Parallel Port Bit Assignments
40
Table 3-11 Parallel Port Addresses
40
Table 3-12 Parallel Port Status Register Bit Assignments
40
Z8536 Counter I/O Unit (Cio)
41
Counter/Timers
41
Table 3-13 Parallel Port Control Register Bit Assignments
41
Table 3-14 CIO Register Address
41
CIO Port a
42
CIO Port B
43
CIO Port C
44
Non-Volatile Parameter Memory
44
Squall II Module Interface
44
Table 3-17 Available Squall II Modules
45
Table 3-18 Squall Module Compatibility at Maximum CPU Clock Speed (33 Mhz)
45
PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)
46
PCI 9060 Configuration
46
Accessing Configuration Registers
47
PCI-To-Local Configuration
48
Table 3-19 Local Configuration Registers
48
RAM Region Configuration
49
Table 3-20 PCI Configuration Registers
49
Table 3-21 Memory Region 0 Settings
50
Table 3-22 Local Address Space 0 Range Register
50
Table 3-23 Local Address Space 0 Local Base Address (Re-Map) Register Description
50
Table 3-24 Local Bus Region Descriptor for PCI-To-Local Access Register Description
51
Expansion ROM Region Configuration
52
Memory Region Configuration Examples
52
Table 3-25 ROM Region Settings
52
Table 3-26 Local Expansion ROM Local Base Address (Re-Map) and Breqo Register Description
53
Table 3-27 Local Expansion ROM Range Register Description
53
Local-To-PCI Configuration
54
Table 3-28 Local Range Register for Direct Master-To-PCI Description
55
Table 3-29 PCI Base Address (Re-Map) Register for Direct Master-To-PCI Description
55
Table 3-30 Local Bus Base Address Register for Direct Master-To-PCI Memory
56
Table 3-31 Local Base Address for Direct Master-To-PCI IO/CFG Register
56
Deadlock Configuration
57
Table 3-32 PCI Configuration Address Register for Direct Master-To-PCI IO/CFG
57
Signalling Init Done
58
PCI Interrupts
58
Local PCI Interrupts
59
Table 3-33 Interrupt Control/Status
59
Mailbox Registers and Doorbell Interrupts
61
Using the Mailbox Registers
61
Generating Doorbell Interrupts
61
Receiving Doorbell Interrupts
61
DMA Programming
62
DMA Non-Chaining Mode
62
DMA Chaining Mode
63
DMA Interrupts
64
Chapter 4 Theory of Operation
65
Functional Overview
67
Clock Generation
67
Power Monitor and Reset
68
I/O Interface
68
Functional Blocks
69
I/O Control Timing
69
Data Path
70
Parallel Port
71
Serial Port
72
Dram Subsystem
72
Page Mode DRAM SIMM Review
72
Bank Interleaving
73
Wait State Performance
73
DRAM Controller Implementation
74
Table 4-1 DRAM Profiles
74
CAS Generation
76
Refresh Generation
76
Chapter 5 Squall II Module Interface
77
Physical Attributes
79
Power Requirements
81
Squall II Module Serial EEPROM
81
Table 5-1 Power Supply
81
Squall II Module Signal Definitions
82
Squall Module Signal Descriptions
83
Table 5-2 Pin Description Nomenclature
83
Table 5-3 Squall Module Signal Descriptions
83
Squall II Module Timing
86
Squall II Module Slave Timing
86
Table 5-4 Squall II Module Slave Timing
87
Squall II Module Master Timing
90
Table 5-5 Squall II Module Master Timing
91
Squall II Module Connector
95
Table 5-6 Squall II Module Pin Assignments
95
Squall II Module Signal Loading and Logic Selection
96
Squall II Module Clock Termination
96
Table 5-7 Squall II Module Signal Loading
96
Appendix A
97
Parts List
97
Table A-1 Cyclone EP/PCI-SDK Platform Bill of Materials
99
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Intel i960 Series Specifications
General
Brand
Intel
Model
i960 Series
Category
Computer Hardware
Language
English
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