Intel S1200V3RP - Page 243

Intel® Server Board S1200V3RP TPS Appendix B: Integrated BMC Sensor Tables
Revision 1.2
229
Full Sensor
Name
(Sensor name
in SDR)
Se
ns
or
#
Platform
Applicabilit
y
Sensor
Type
Event/R
eading
Type
Event Offset Triggers
Contrib.
To
System
Status
Assert
/De-
assert
Reada
ble
Value/
Offset
s
Event
Data
Rearm
St
an
db
y
Thermal
Margin
(P4 Therm
Margin)
h
specific
ature
01h
old
01h
g
Processor 1
Thermal
Control %
(P1 Therm
Ctrl %)
78
h
All
Temper
ature
01h
Thresh
old
01h
[u] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
Trig
Offset
A
–
Processor 2
Thermal
Control %
(P2 Therm
Ctrl %)
79
h
All
Temper
ature
01h
Thresh
old
01h
[u] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
Trig
Offset
A
–
Processor 3
Thermal
Control %
(P3 Therm
Ctrl %)
7
A
h
Platform-
specific
Temper
ature
01h
Thresh
old
01h
[u] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
Trig
Offset
A
–
Processor 4
Thermal
Control %
(P4 Therm
Ctrl %)
7
B
h
Platform-
specific
Temper
ature
01h
Thresh
old
01h
[u] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
Trig
Offset
A
–
Processor 1
ERR2
Timeout
(P1 ERR2)
7
C
h
All
Proces
sor
07h
Digital
Discret
e
03h
01 – State Asserted
fatal
As
and
De
–
Trig
Offset
A
–
Processor 2
ERR2
Timeout
(P2 ERR2)
7
D
h
All
Proces
sor
07h
Digital
Discret
e
03h
01 – State Asserted
fatal
As
and
De
–
Trig
Offset
A
–
Processor 3
ERR2
Timeout
(P3 ERR2)
7
E
h
Platform-
specific
Proces
sor
07h
Digital
Discret
e
03h
01 – State Asserted
fatal
As
and
De
–
Trig
Offset
A
–
Processor 4
ERR2
Timeout
(P4 ERR2)
7
F
h
Platform-
specific
Proces
sor
07h
Digital
Discret
e
03h
01 – State Asserted
fatal
As
and
De
–
Trig
Offset
A
–
Catastrophic
Error
(CATERR)
80
h
All
Proces
sor
07h
Digital
Discret
e
03h
01 – State Asserted
fatal
As
and
De
–
Trig
Offset
M
–
Processor1
81
All
Proces
Digital
01 – State Asserted
fatal
As
–
Trig
M
–