Intel S1200V3RP - Page 250

Appendix B: Integrated BMC Sensor Tables Intel® Server Board S1200V3RP TPS
Revision 1.2
236
Full Sensor
Name
(Sensor name
in SDR)
Se
ns
or
#
Platform
Applicabilit
y
Sensor
Type
Event/R
eading
Type
Event Offset Triggers
Contrib.
To
System
Status
Assert
/De-
assert
Reada
ble
Value/
Offset
s
Event
Data
Rearm
St
an
db
y
+1.05Vccp
P1)
fatal
Baseboard
+1.05V
Processor2
Vccp
(BB
+1.05Vccp
P2)
D
7h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
+1.5V P1
Memory AB
VDDQ
(BB +1.5
P1MEM AB)
D
8h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
+1.5V P1
Memory CD
VDDQ
(BB +1.5
P1MEM CD)
D
9h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
+1.5V P2
Memory AB
VDDQ
(BB +1.5
P2MEM AB)
D
A
h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
+1.5V P2
Memory CD
VDDQ
(BB +1.5
P2MEM CD)
D
B
h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
+1.8V Aux
(BB +1.8V
AUX)
D
C
h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
+1.1V
Stand-by
(BB +1.1V
STBY)
D
D
h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
fatal
As
and
De
Analo
g
R, T
A
–
Baseboard
CMOS
Battery
(BB +3.3V
Vbat)
D
E
h
All
Voltage
02h
Thresh
old
01h
[u,l] [c,nc]
nc =
Degrad
ed
c =
Non-
As
and
De
Analo
g
R, T
A
–