*SRE <enable>
*SRE?
Service Request Enable Command and Query. Enable register for the Status Byte Register. Once enabled, the cor-
responding bits may generate a Request for Service (RQS) in the Status Byte. This RQS event may generate a "call
back" to your application as a type of asynchronous interrupt.
Parameter Typical return
Decimal sum of the bits in the register.
For example, to enable bit 2 (decimal value = 4), bit 3 (decimal value = 8), and
bit 7 (decimal value = 128), the decimal sum would be 140 (4 + 8 + 128).
Default: 0
+16
Enables bit 4 (decimal value = 16) in the enable register: *SRE 16
– To enable specific bits, specify the decimal value corresponding to the binary-weighted sum of the bits in the
register. The selected bits are summarized in the "Master Summary" bit (bit 6) of the Status Byte Register. If any
of the selected bits change from 0 to 1, the instrument generates a Service Request signal.
– *CLS command clears the event register, but does not clear the enable register. An event register is a read-only
register that latches events from the condition register. While an event bit is set, subsequent events cor-
responding to that bit are ignored.
– Use *PSC to control whether the Status Byte enable register is cleared at power-on. For example, *PSC 0 pre-
serves the enable register contents through power cycles.
–
The <enable> setting is non-volatile; it does not change after a Factory Reset (*RST command) , Instrument Pre-
set (SYSTem:PRESet command), Status Preset (STATus:PRESet command) or Clear Status (*CLS command).
*STB?
Read Status Byte Query. Queries the condition register for the Status Byte Register group and returns a decimal
value equal to the binary-weighted sum of all bits set in the register. A condition register continuously monitors the
state of the instrument. Condition register bits are updated in real time; they are neither latched nor buffered.
Parameter Typical return
(none) +40
Reads the condition register when bits 3 and 5 are set: *STB?
– This query returns the same results as a Serial Poll but the "Master Summary" bit (bit 6) is not cleared if a Serial
Poll has occurred.
– Unlike how a reset clears the condition register, a factory reset (*RST) does not clear the Status Byte Register.
152
Keysight DAQ970A/DAQ973A Programming Guide
2 SCPI Programming
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