Issue 1 December 1997 xxxi
Figures
5 Transmission and Synchronization Interfaces
5-1 OC-12 Multiplexer Block Diagram — STS-1/
VT1.5 Path Switched Ring Node 5-3
5-2 OC-3/OC-12 Ring (0x1) Low-Speed Interfaces
Single Homing 5-5
5-3 OC-3/OC-12 Ring Low-Speed Interfaces (0x1)
Dual Homing 5-7
5-4 OC-12 Ring Shelf with Linear (1+1) OC-3 Low-
Speed Interfaces (Transmit) 5-8
5-5 OC-12 Ring Shelf with Linear (1+1) OC-3 Low-
Speed Interfaces (Receive) 5-9
5-6 Synchronization Timing Configurations 5-13
5-7 DS1 Timing Output — Dual Homing Linear 5-18
5-8 Synchronization Reconfiguration — Access Ring 5-20
5-9 Synchronization Reconfiguration — Externally
Timed Access Ring 5-25
5-10 Synchronization Reconfiguration — Access Ring 5-27
5-11 OC-N Derived DS1 Timing Reference 5-31
5-12 Timing from Multiplexed DS1 5-33
6 Operations Interfaces
6-1 Craft Interface Terminal Connectors 6-4
6-2 Craft Interface Terminal Login Sessions 6-5
6-3 User Panel for Group 4 Shelf 6-9
6-4 Miscellaneous Discretes 6-17
7 Circuit Pack Descriptions
7-1 Universal Optical Connector 7-3
7-2 BBG8/BBG8B SYSCTL Circuit Pack 7-5
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