NCR RealPOS 70 - Page 260

12-20 Chapter 12: Cash Drawer Interface
// The BIOS assigns these addresses dynamically. We obtain the addresses as
// follows:
//
// A. Write to m_nIOConf, then read GPIOBASE from m_nIOConf+4 and add the
respective
// offset to the result to obtain m_nIOPort and m_nIOPort_select.
// B. We can now control the solenoid bits and read the status bit via
m_nIOPort
// and Input/Output select via m_nIOPort_select.
// (see ReadInPort() and WriteOutPort() for details)
//
// REFERENCES: Shanley/Anderson, "PCI System Architecture" 3rd. ed. (Chapter
15-17)
// "INTEL ICH4 I/O Controller Hub" Datasheet
BOOL QueryConf()
{
BOOL result = TRUE;
DWORD FileOffset=0x40;
DWORD DataRead=0;
// Configuration Address Register at 0x0CF8
// bit 31 = 1 ; Enable Configuration Space Mapping
// bits 30 - 24 = 0 ; Reserved
// bits 23 - 16 = 0 ; Bus number
// bits 15 - 11 = 31 ; Device
// bits 10 - 8 = 0 ; Function
// bits 7 - 0 = 58; Register bits 1 - 0 Always zero (See NOTE 1)
// NOTE 1: GPIO base Address is read from General Purpose I/O Register Base
Address at a fixed Offset = 0x58
// The GPIO Register Base Address value provides a base address in bits 15:6.
Therefore mask is 0x0FFC0.
DWORD n_configGPIOReqData = 0x8000F858; // Dev. 31, Func. 0, Reg. 0x58
DWORD gpioport=0;
UCHAR uc_gp_offset = 0x38; //DWORD IOoffset for the GPIO solenoid and status
bits
// GPI[34:32] are bits 2:0
UCHAR uc_gpsel_offset = 0x34; //DWORD IOoffset for the GPIO select
register
// GPO[34:32] are bits 2:0
UCHAR uc_gpuse_offset = 0x30; // IOoffset for GPIO Use select reg, 1 = GPIO
int CD7402USE_GPIO = 0x0000000F;
WORD nUsePort =0;
UCHAR status_mask = 0x01; // GPI[32]
UCHAR solenoidA_mask = 0x02; // GPO[33]
UCHAR solenoidB_mask = 0x04; // GPO[34]
DWORD DataWritten=0;