NXP Semiconductors MPC5777M - Page 122

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors122
5 — CC Clock high time 4 — PER_CLK Cycle
6 — CC Data setup time 0.0 — ns
7 — CC Start condition setup time (for repeated start condition only) 2 — PER_CLK Cycle
8 — CC Stop condition setup time 2 — PER_CLK Cycle
1
I
2
C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower
than 1 ns (10% – 90%).
2
PER_CLK is the SoC peripheral clock, which drives the I
2
C BIU and module clock inputs. See the Clocking chapter in
the device reference manual for more detail.
Table 71. I
2
C output timing specifications — SCL and SDA
1,2 ,3,4
No. Symbol Parameter
Value
Unit
Min Max
1 — CC Start condition hold time 6 — PER_CLK Cycle
5
2 — CC Clock low time 10 — PER_CLK Cycle
3 — CC Bus free time between Start and Stop condition 4.7 — µs
4 — CC Data hold time 7 — PER_CLK Cycle
5 — CC Clock high time 10 — PER_CLK Cycle
6 — CC Data setup time 2 — PER_CLK Cycle
7 — CC Start condition setup time (for repeated start condition only) 20 — PER_CLK Cycle
8 — CC Stop condition setup time 10 — PER_CLK Cycle
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2
Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and
may cause incorrect operation.
4
Programming the IBFD register (I
2
C bus Frequency Divider) with the maximum frequency results in the minimum
output timings listed. The I
2
C interface is designed to scale the data transition time, moving it to the middle of the SCL
low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD
register.
5
PER_CLK is the SoC peripheral clock, which drives the I
2
C BIU and module clock inputs. See the Clocking chapter
in the device reference manual for more detail.
Table 70. I
2
C input timing specifications — SCL and SDA
1
(continued)
No. Symbol Parameter
Value
Unit
Min Max