MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors132
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm
2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T
J
= T
B
+ (R
JB
* P
D
) Eqn. 2
where:
T
B
= board temperature for the package perimeter (
o
C)
R
JB
= junction-to-board thermal resistance (
o
C/W) per JESD51-8
P
D
= power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable
if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
R
JA
= R
JC
+ R
CA
Eqn. 3
where:
R
JA
= junction-to-ambient thermal resistance (
o
C/W)
R
JC
= junction-to-case thermal resistance (
o
C/W)
R
CA
= case to ambient thermal resistance (
o
C/W)
R
JC
is device related and is not affected by other factors. The thermal environment can be controlled to change the
case-to-ambient thermal resistance, R
CA
. For example, change the air flow around the device, add a heat sink, change the
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
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