NXP Semiconductors MPC5777M - Page 56

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors56
TUE
12
CC TUE degradation due
to V
DD_HV_ADR_S
offset
with respect to
V
DD_HV_ADV_S
V
IN
< V
DD_HV_ADV_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[0:25 mV]
00LSB
(12b)
V
IN
< V
DD_HV_ADV_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[25:50 mV]
–2 2
V
IN
< V
DD_HV_ADV_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[50:75 mV]
–4 4
V
IN
< V
DD_HV_ADV_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[75:100 mV]
–6 6
V
DD_HV_ADV_S
< V
IN
<
V
DD_HV_ADR_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[0:25 mV]
–2.5 2.5
V
DD_HV_ADV_S
< V
IN
<
V
DD_HV_ADR_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[25:50 mV]
–4 4
V
DD_HV_ADV_S
< V
IN
<
V
DD_HV_ADR_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[50:75 mV]
–7 7
V
DD_HV_ADV_S
< V
IN
<
V
DD_HV_ADR_S
V
DD_HV_ADR_S
 V
DD_HV_ADV_S

[75:100 mV]
–12 12
DNL CC Differential
non-linearity
V
DD_HV_ADV_S
> 4 V
V
DD_HV_ADR_S
> 4 V
–1 2 LSB
(12b)
INL CC Integral non-linearity 4.0 V < V
DD_HV_ADV_S
< 5.5 V
4.0 V < V
DD_HV_ADR_S
< 5.5 V
–3 3 LSB
(12b)
V
DD_HV_ADV_S
= 2V
V
DD_HV_ADR_S
= 2 V
–5 5
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB
within the sampling window. Please refer to Figure 14 and Figure 15 for models of the internal ADC circuit, and the
values to use in external RC sizing and calculating the sampling window duration.
3
I
ADCREFH
and I
ADCREFL
are independent from ADC clock frequency. It depends on conversion rate: consumption is
driven by the transfer of charge between internal capacitances during the conversion.
4
Current parameter values are for a single ADC.
5
Extra bias current is present only when BIAS is selected.
Table 27. SARn ADC electrical specification
1
(continued)
Symbol Parameter Conditions
Value
Unit
Min Max