Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 91
3.16.1.4 Aurora debug port timing
3
Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
Table 49. Aurora debug port timing
# Symbol Characteristic
Value
Unit
Min Max
1t
REFCLK
CC Reference clock frequency 625 1250 MHz
1a t
MCYC
CC Reference clock rise/fall time — 400 ps
2t
RCDC
CC Reference clock duty cycle 45 55 %
3J
RC
CC Reference clock jitter — 40 ps
4t
STABILITY
CC Reference clock stability 50 — PPM
5 BER CC Bit error rate — 10
–12
—
6J
D
SR Transmit lane deterministic jitter — 0.17 OUI
7J
T
SR Transmit lane total jitter — 0.35 OUI
8S
O
CC Differential output skew — 20 ps
9S
MO
CC Lane to lane output skew — 1000 ps
10 OUI CC Aurora lane unit interval
1
1
± 100 PPM
625 Mbps 1600 1600 ps
1.25 Gbps 800 800
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